Datasheet AD9057 (Analog Devices) - 9

AD9057
The AD9057 provides high impedance digital output operation full-power analog bandwidth of 2¥ the maximum sampling rate, when the ADC is driven into power-down mode (PWRDN, logic the ADC provides sufficient pixel-to-pixel transient settling time high). A 200 ns (minimum) power-down time should be to ensure accurate 60 MSPS video digitization. Figure 5 shows a provided before a high impedance characteristic is required at typical RGB video digitizer implementation for the AD9057. the outputs. A 200 ns power-up period should be provided to ensure accurate ADC output data after reactivation (valid out-
8
put data is available three clock cycles after the 200 ns delay).
RED AD9057 Timing 8
The AD9057 is guaranteed to operate with conversion rates from
GREEN AD9057
5 MSPS to 80 MSPS depending on grade. The ADC is designed to operate with an encode duty cycle of 50%, but performance
8 BLUE AD9057
is insensitive to moderate variations. Pulsewidth variations of up to ± 10% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degradation in
PIXEL CLOCK
ADC performance (see Figure 1 timing diagram).
H-SYNC PLL Power Dissipation
Figure 5. RGB Video Encoder The power dissipation of the AD9057 is specified to reflect a
Evaluation Board
typical application setup under the following conditions: analog The AD9057/PCB evaluation board provides an easy-to-use input is –0.5 dBFS at 10.3 MHz, VD is 5 V, VDD is 3 V, and digital analog/digital interface for the 8-bit, 60 MSPS ADC. The board outputs are loaded with 7 pF typical (10 pF maximum). The includes typical hardware configurations for a variety of high actual dissipation will vary as these conditions are modified in speed digitization evaluations. On-board components include user applications. TPC 7 shows typical power consumption for the the AD9057 (in the 20-lead SSOP package), an optional analog AD9057 versus ADC encode frequency and VDD supply voltage. input buffer amplifier, a digital output latch, board timing drivers, A power-down function allows users to reduce power dissipation an analog reconstruction digital-to-analog converter, and config- when ADC data is not required. A TTL/CMOS high signal urable jumpers for ac coupling, dc coupling, and power-down (PWRDN) shuts down portions of the ADC and brings total function testing. The board is configured at shipment for dc power dissipation to less than 10 mW. The internal band gap coupling using the AD9057’s internal voltage reference. voltage reference remains active during power-down mode to For dc-coupled analog input applications, amplifier U2 is con- minimize ADC reactivation time. If the power-down function is figured to operate as a unity gain inverter with adjustable offset not desired, Pin 1 should be tied to ground. for the analog input signal. For full-scale ADC drive, the analog input signal should be 1 V p-p into 50 W (R1) referenced to
APPLICATIONS
ground (0 V). The amplifier offsets the analog signal by +VREF The wide analog bandwidth of the AD9057 makes it attractive for (2.5 V typical) to center the voltage for proper ADC input drive. a variety of high performance receiver and encoder applications. For dc-coupled operation, connect E1 to E2 (analog input to Figure 4 shows two ADCs in a typical low cost I and Q demodula- R2) and E11 to E12 (amplifier output to analog input of AD9057) tor implementation for cable, satellite, or wireless LAN modem using the board jumper connectors. DC offset of the analog receivers. The excellent dynamic performance of the ADC at input signal can be modified by adjusting potentiometer R10. higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques (refer to TPC 2 For ac-coupled analog input applications, amplifier U2 is spectral plot). IF sampling eliminates or simplifies analog mixer removed from the analog signal path. The analog signal is and filter stages to reduce total system cost and power. coupled into the input of the AD9057 through capacitor C2. The ADC pulls analog input bias current from the VREF IN voltage through the 1 kW resistor internal to the AD9057 (BIAS
BPF AD9057
OUT). The analog input signal to the board should be 1 V p-p into 50 W (R1) for full-scale ADC drive. For ac-coupled operation,
IF IN 90
connect E1 to E3 (analog input A to C2 feedthrough capacitor)
BPF AD9057
and E10 to E12 (C2 to the analog input and internal bias resis- tor) using the board jumper connectors. The on-board reference voltage may be used to drive the ADC
VCO VCO
or an external reference may be applied. To use the internal Figure 4. I and Q Digital Receiver voltage reference, connect E6 to E5 (VREF OUT to VREF IN). To apply an external voltage reference, connect E4 to E5 The high sampling rate and analog bandwidth of the AD9057 (external reference from the REF banana jack to VREF IN). are ideal for computer RGB video digitizer applications. With a The external voltage reference should be 2.5 V ± 10%. –8– REV. D Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9057 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation APPLICATIONS Evaluation Board OUTLINE DIMENSIONS Revision History