Datasheet AD9057 (Analog Devices) - 4

AD9057 Test AD9057BRS-40 AD9057BRS-60 AD9057BRS-80 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3 V) Full VI 2.95 2.95 2.95 V Logic 1 Voltage (VDD = 5 V) Full IV 4.95 4.95 4.95 V Logic 0 Voltage Full VI 0.05 0.05 0.05 V Output Coding Offset Binary Code Offset Binary Code Offset Binary Code POWER SUPPLY VD Supply Current (VD = 5 V) Full VI 36 48 38 48 40 51 mA VDD Supply Current (VDD = 3 V)4 Full VI 4.0 6.5 5.5 6.5 7.4 8.8 mA Power Dissipation5, 6 Full VI 192 260 205 260 220 281 mW Power-Down Dissipation Full VI 6 10 6 10 6 10 mW Power Supply Rejection Ratio (PSRR) 25∞C V 3 3 3 mV/V NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 2tV and tPD are measured from the 1.5 V level of the encode to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 mA. 3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range. 4Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions. 5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = 5 V ± 5%, VDD = 3 V ± 5%). 6Typical thermal impedance for the RS style (SSOP) 20-lead package : qJC = 46∞C/W, qCA = 80∞C/W, and qJA = 126∞C/W. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS Test Level Description
I 100% production tested. II 100% production tested at 25∞C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and charac- terization testing. V Parameter is a typical value only. VI 100% production tested at 25∞C; guaranteed by design and characterization testing for industrial temperature range.
N N + 3 N + 5 AIN N + 1 N + 2 N + 4 tA ENCODE tEH tEL tV DIGITAL N – 3 N – 2 N – 1 N N + 1 N + 2 OUTPUTS tPD MIN TYP MAX tA APERTURE DELAY 2.7 ns tEH PULSEWIDTH HIGH 166 ns tEL PULSEWIDTH LOW 166 ns tV OUTPUT VALID TIME 4.0 ns 6.6 ns tPD OUTPUT PROP DELAY 9.5 ns
Figure 1. Timing Diagram REV. D –3– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9057 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation APPLICATIONS Evaluation Board OUTLINE DIMENSIONS Revision History