Datasheet AD7851 (Analog Devices) - 7

AD7851 TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
1.6mA IOL
Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of
TO
285 kHz in Interface Modes 2 and 3, reading and writing must
2.1V OUTPUT
be performed during conversion. Figure 3 shows the timing dia-
CL PIN 50pF
gram for Interface Modes 4 and 5 with sample rate of 285 kHz. At least a 330 ns acquisition time must be allowed (the time
200µA I
from the falling edge of BUSY to the next rising edge of
OH
CONVST) before the next conversion begins to ensure that the part is settled to the 14-bit level. If the user does not want to Figure 1. Load Circuit for Digital Output Timing provide the CONVST signal, the conversion can be initiated in Specifications software by writing to the control register.
POLARITY PIN LOGIC HIGH t = 3.25µs MAX, t = 100ns MIN, CONVERT 1 t = 30ns MAX, t = 30ns MIN 5 7 t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t3 t t 9 11 SCLK (I/P) 1 5 6 16 t t 5 10 t t 6 t12 6 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB11 DB0 t7 t8 DIN (I/P) DB15 DB11 DB0
Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH t = 3.25µs MAX, t = 100ns MIN, CONVERT 1 t = 30ns MAX, t = 30ns MIN 5 7 t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC
(
O/P) t4 t t 9 11 SCLK (O/P) 1 5 6 16 t t 5 10 t t 6 12 THREE-STATE THREE-STATE DOUT (O/P) DB15 DB11 DB0 t7 t8 DIN (I/P) DB15 DB11 DB0
Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5) –6– REV. B Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS SPECIFICATIONS TIMING SPECIFICATIONS TYPICAL TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS PINOUT FOR DIP, SOIC, AND SSOP ORDERING GUIDE TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error Unipolar Offset Error Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Power Supply Rejection Ratio (PSRR) Full Power Bandwidth (FPBW) PIN FUNCTION DESCRIPTIONS AD7851 ON-CHIP REGISTERS Addressing the On-Chip Registers Writing Reading CONTROL REGISTER STATUS REGISTER CALIBRATION REGISTERS Addressing the Calibration Registers Writing to/Reading from the Calibration Registers Adjusting the Offset Calibration Register Adjusting the Gain Calibration Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUT Acquisition Time DC/AC Applications Input Ranges Transfer Functions REFERENCE SECTION AD7851 PERFORMANCE CURVES POWER-DOWN OPTIONS POWER-UP TIMES Using an External Reference Using the Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE CALIBRATION SECTION Calibration Overview Automatic Calibration on Power-On Self-Calibration Description Self-Calibration Timing System Calibration Description System Gain and Offset Interaction System Calibration Timing SERIAL INTERFACE SUMMARY Resetting the Serial Interface DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) MODE 4 and 5 (Self-Clocking Modes) CONFIGURING THE AD7851 AD7851 as a Read-Only ADC Writing to the AD7851 Interface Modes 2 and 3 Configuration Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration MICROPROCESSOR INTERFACING AD7851 to 8XC51/PIC17C42 Interface AD7851 to 68HC11/16/L11/PIC16C42 Interface AD7851 to ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface AD7851 to TMS320C20/25/5x/LC5x Interface APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance AD785x Family OUTLINE DIMENSIONS Revision History