Datasheet AD7851 (Analog Devices) - 4

AD7851 SPECIFICATIONS1, 2 A Grade: fCLKIN = 7 MHz (–40
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C to +85
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C), fSAMPLE = 333 kHz; K Grade: fCLKIN = 6 MHz (0
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C to 85
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C), fSAMPLE = 285 kHz; A and K Grade: fCLKIN = 5 MHz (to 125
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C), fSAMPLE = 238 kHz; (AVDD = DVDD = 5.0 V
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5%, REFIN/REFOUT = 4.096 V External Reference; SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Parameter Version A1 Version K1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE Signal-to-Noise + Distortion Ratio3 (SNR) 77 78 dB min Typically SNR Is 79.5 dB. VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz. Total Harmonic Distortion (THD) –86 –86 dB max VIN = 10 kHz, Sine Wave, fSAMPLE = 333 kHz, typically –96 dB. Peak Harmonic or Spurious Noise –87 –87 dB max VIN = 10 kHz, fSAMPLE = 333 kHz. Intermodulation Distortion (IMD) Second-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz. Third-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz. Full Power Bandwidth 20 20 MHz typ @ 3 dB. DC ACCURACY Resolution 14 14 Bits Integral Nonlinearity ±2 ±1 LSB max Differential Nonlinearity ±2 ±1 LSB max Guaranteed No Missed Codes to 14 Bits Unipolar Offset Error ±10 ±10 LSB max Review: Adjusting the Offset Calibration Positive Full-Scale Error ±10 ±10 LSB max Register in the Calibration Registers section. Negative Full-Scale Error ±10 ±10 LSB typ Bipolar Zero Error ±1 ±1 LSB typ ANALOG INPUT Input Voltage Ranges 0 V to VREF 0 V to VREF V AIN(+) – AIN(–) = 0 V to VREF, AIN(–) can be biased up but AIN(+) cannot go below AIN(–). ±VREF/2 ±VREF/2 V AIN(+) – AIN(–) = –VREF/2 to +VREF/2, AIN(–) should be biased up and AIN(+) can go below AIN(–) but cannot go below 0 V. Leakage Current ±1 ±1 µA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REFIN Input Voltage Range 4/VDD 4/VDD V min/max Functional from 1.2 V. Input Impedance 150 150 kΩ typ Resistor Connected to Internal Reference Node. REFOUT Output Voltage 3.696/4.496 3.696/4.496 V min/max REFOUT Temperature Coefficient 50 50 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH VDD – 1.0 VDD – 1.0 V min Input Low Voltage, VINL 0.4 0.4 V max Input Current, I ± IN 10 ±10 µA max VIN = 0 V or VDD. Input Capacitance, C 4 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD – 0.4 VDD – 0.4 V min ISOURCE = 200 µA. Output Low Voltage, VOL 0.4 0.4 V max ISINK = 0.8 mA. Floating State Leakage Current ±10 ±10 µA max Floating State Output Capacitance4 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range. Twos Complement Bipolar Input Range. CONVERSION RATE Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles. Conversion + Track-and-Hold Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate. REV. B –3– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS SPECIFICATIONS TIMING SPECIFICATIONS TYPICAL TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS PINOUT FOR DIP, SOIC, AND SSOP ORDERING GUIDE TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error Unipolar Offset Error Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Power Supply Rejection Ratio (PSRR) Full Power Bandwidth (FPBW) PIN FUNCTION DESCRIPTIONS AD7851 ON-CHIP REGISTERS Addressing the On-Chip Registers Writing Reading CONTROL REGISTER STATUS REGISTER CALIBRATION REGISTERS Addressing the Calibration Registers Writing to/Reading from the Calibration Registers Adjusting the Offset Calibration Register Adjusting the Gain Calibration Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUT Acquisition Time DC/AC Applications Input Ranges Transfer Functions REFERENCE SECTION AD7851 PERFORMANCE CURVES POWER-DOWN OPTIONS POWER-UP TIMES Using an External Reference Using the Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE CALIBRATION SECTION Calibration Overview Automatic Calibration on Power-On Self-Calibration Description Self-Calibration Timing System Calibration Description System Gain and Offset Interaction System Calibration Timing SERIAL INTERFACE SUMMARY Resetting the Serial Interface DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) MODE 4 and 5 (Self-Clocking Modes) CONFIGURING THE AD7851 AD7851 as a Read-Only ADC Writing to the AD7851 Interface Modes 2 and 3 Configuration Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration MICROPROCESSOR INTERFACING AD7851 to 8XC51/PIC17C42 Interface AD7851 to 68HC11/16/L11/PIC16C42 Interface AD7851 to ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface AD7851 to TMS320C20/25/5x/LC5x Interface APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance AD785x Family OUTLINE DIMENSIONS Revision History