Datasheet AD7823 (Analog Devices) - 9

AD7823 POWER-UP TIMES OPERATING MODES
The AD7823 has a 1.5 µs power-up time. When VDD is first
Mode 1 Operation (High Speed Sampling)
connected, the AD7823 is in a low current mode of operation. When the AD7823 is used in this mode of operation, the part is In order to carry out a conversion, the AD7823 must first be not powered down between conversions. This mode of opera- powered up. The ADC is powered up by a rising edge on the tion allows high throughput rates to be achieved. The timing CONVST pin. A conversion is initiated on the falling edge of diagram in Figure 14 shows how this optimum throughput rate CONVST. Figure 12 shows how to power up the AD7823 when is achieved by bringing the CONVST signal high before the end VDD is first connected or after the AD7823 is powered down of the conversion. It is recommended that the CONVST signal using the CONVST pin. should go high within 3 µs of conversion starting. This ensures Care must be taken to ensure that the CONVST pin of the that the CONVST signal does not go high at the same time the AD7823 is logic low when V part is attempting to power down. The AD7823 leaves its tracking DD is first applied. mode and goes into hold on the falling edge of CONVST. A conversion is also initiated at this time and takes 4 µs typ to
MODE 1 ( CONVST IDLES HIGH)
complete. At this point, the result of the current conversion is
VDD tPOWER-UP 1µs
latched into the serial shift register, and the state of the CONVST
1.5
␮
s
signal is checked. The CONVST signal should be high at the
CONVST
end of the conversion to prevent the part from powering down.
MODE 2 ( CONVST IDLES LOW) t1 VDD tPOWER-UP CONVST 1.5
␮
s t A CONVST B 2 SCLK
Figure 12. Power-Up Times
D CURRENT CONVERSION OUT POWER VS. THROUGHPUT RATE RESULT
By operating the AD7823 in Mode 2, the average power con- Figure 14. Mode 1 Operation Timing sumption of the AD7823 decreases at lower throughput rates. Figure 13 shows how the automatic power-down is implemented The serial port on the AD7823 is enabled on the rising edge of using the CONVST signal to achieve the optimum power per- the CONVST signal–see Serial Interface section. As explained formance for the AD7823. The AD7823 is operated in Mode 2. earlier, this rising edge should occur before the end of the con- As the throughput rate is reduced, the device remains in its version process if the part is not to be powered down. A serial power-down state for longer, and the average power consump- read can take place at any stage after the rising edge of CONVST. tion over time drops accordingly. If a serial read is initiated before the end of the current conver- sion process (i.e., at time “A”), then the result of the previous
t
conversion is shifted out on the D
CONVERT
OUT pin. It is possible to allow
5
␮
s t
the serial read to extend beyond the end of a conversion. In this
POWER-UP 1.5
␮
s POWER-DOWN
case, the new data will not be latched into the output shift regis-
CONVST
ter until the read has finished. If the user waits until the end of the conversion process, i.e., 4 µs typ after falling edge of CONVST
tCYCLE
(Point “B”), before initiating a read, the current conversion
100
␮
s @ 10kSPS
result is shifted out. Figure 13. Automatic Power-Down For example, if the AD7823 is operated in a continuous sampling mode with a throughput rate of 10 kSPS, the power consumption is calculated as follows. The power dissipation during normal operation is 10.5 mW, VDD = 3 V. If the power-up time is 1.5 µs and the conversion time is 5 µs, then the AD7823 can be said to dissipate 10.5 mW for 6.5 µs (worst case) during each conver- sion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs, and the average power dissipated during each cycle is (6.5/100) × (10.5 mW) = 683 µW. Figure 2 shows a graph of Power vs. Throughput. –8– REV. C