Datasheet AD9240 (Analog Devices) - 9

AD9240 INTRODUCTION 80 RBIAS =
The AD9240 uses a four-stage pipeline architecture with a
2k
V
70
wideband input sample-and-hold amplifier (SHA) implemented
RBIAS = 4k
V on a cost-effective CMOS process. Each stage of the pipeline,
60
excluding the last, consists of a low resolution flash A/D con-
50
nected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the differ-
40 RBIAS = 10k
V ence between the reconstructed DAC output and the flash input
SINAD – dB
for the next stage in the pipeline. One bit of redundancy is used
30 RBIAS = 20k
V in each of the stages to facilitate digital correction of flash er-
20 RBIAS = 200k
V rors. The last stage simply consists of a flash A/D.
10
The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the
0 1 10 20
converter is capable of capturing a new input sample every clock
CLOCK FREQUENCY – MHz
cycle, it actually takes three clock cycles for the conversion to be Figure 21. SINAD vs. Clock Frequency for Varying R fully processed and appear at the output. This latency is not a BIAS Values (V concern in most applications. The digital output, together with CM = 2.5 V, AIN = –0.5 dB, 5 V Span, fIN = fCLK/2) the out-of-range indicator (OTR), is latched into an output
400
buffer to drive the output pins. The output drivers can be con- figured to interface with +5 V or +3.3 V logic families.
350
The AD9240 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing V
300 = 1.7k RBIAS
requirements). The A/D samples the analog input on the rising
= 2k
V
RBIAS
edge of the clock input. During the clock low time (between the V
250 = 2.5k
falling edge and rising edge of the clock), the input SHA is in
RBIAS
V
= 3.3k
the sample mode; during the clock high time it is in the hold
R POWER – mW BIAS 200 = 5k
V mode. System disturbances just prior to the rising edge of the
RBIAS
V clock and/or excessive clock jitter may cause the input SHA to
R = 10k BIAS
acquire the wrong value, and should be minimized.
150
V
= 100k RBIAS Speed/Power Programmability 100
The AD9240’s maximum conversion rate and associated power
2 4 6 8 10 12 14 16 18 20 CLOCK FREQUENCY – MHz
dissipation can be set using the part’s BIAS pin. A simplified diagram of the on-chip circuitry associated with the BIAS pin is Figure 22. Power Dissipation vs. Clock Frequency for shown in Figure 20. Varying RBIAS Values
ANALOG INPUT AND REFERENCE OVERVIEW ADCBIAS
Figure 23, a simplified model of the AD9240, highlights the rela- tionship between the analog inputs, VINA, VINB, and the ref-
BIAS
erence voltage, VREF. Like the voltage applied to the top of
RBIAS IFIXED
the resistor ladder in a flash A/D converter, the value VREF defines
AD9240
the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF. Figure 20.
AD9240
The value of RBIAS can be varied over a limited range to set the
VINA +VREF
maximum sample rate and power dissipation of the AD9240. A
VCORE 14 A/D
typical plot of S/(N+D) @ fIN = Nyquist vs. fCLK at varying
CORE
RBIAS is shown in Figure 21. A similar plot of power vs. fCLK at varying RBIAS is shown in Figure 22. These plots indicate
VINB –VREF
typical performance vs. RBIAS. Note that all other plots and specifications in this data sheet reflect performance at a fixed Figure 23. Equivalent Functional Input Circuit RBIAS = 2 kΩ. –8– REV. B