Datasheet AD7864 (Analog Devices) - 8

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AD7864 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS E C 0 1 2 3 4 5 ND IV DD 6 DR EO DB DB DB DB DB DB DG V DV DB 44 43 42 41 40 39 38 37 36 35 34 BUSY 1 33 DB7 FRSTDATA PIN 1 2 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 RD 5 29 DB11 AD7864 WR 6 TOP VIEW 28 CLKIN SL1 7 (Not to Scale) 27 INT/EXT CLK SL2 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF H/S SEL 11 23 VREFGND 12 13 14 15 16 17 18 19 20 21 22 4B 4A 3B 3A 2B 2A 1B 1A Y
03
ND ND B
0
IN IN IN IN IN IN IN IN
1-
V V V V V V V V ST AG AG
134 0 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. 2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data register pointer is addressing Register 1—see the Accessing the Output Data Registers section. 3 CONVST Convert Start Input. Logic input. A low-to-high transition on this input puts all track-and-holds into their hold mode and starts conversion on the selected channels. In addition, the state of the channel sequence selection is also latched on the rising edge of CONVST. 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 RD Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. 6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. 7 to 10 SL1 to SL4 Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if H/S SEL is Logic 0. The selection is latched on the rising edge of CONVST. See the Selecting a Conversion Se sec quence tion. 11 H/S SEL Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection is controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register. See the Selecting a Conversion Sequence section. 12 AGND Analog Ground. General analog ground. Connect this AGND pin to the AGND plane of the system. 13 to 16 VIN4x, VIN3x Analog Inputs. See the Analog Input section. 17 AGND Analog Ground. Analog ground reference for the attenuator circuitry. Connect this AGND pin to the AGND plane of the system. 18 to 21 VIN2x, VIN1x Analog Inputs. See the Analog Input section. 22 STBY Standby Mode Input. TTL-compatible input that is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. 23 VREFGND Reference Ground. This is the ground reference for the on-chip reference buffer of the part. Connect the VREFGND pin to the AGND plane of the system. 24 VREF Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also allows the internal reference to be overdriven by an external reference source (2.5 V). Connect a 0.1 μF decoupling capacitor between this pin and AGND. 25 AVDD Analog Positive Supply Voltage, 5.0 V ± 5%. 26 AGND Analog Ground. Analog ground reference for the DAC circuitry. Rev. D | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Reference CIRCUIT DESCRIPTION ANALOG INPUT AD7864-1 AD7864-2 AD7864-3 SELECTING A CONVERSION SEQUENCE TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence Reading After the Conversion Sequence USING AN EXTERNAL CLOCK STANDBY MODE OPERATION ACCESSING THE OUTPUT DATA REGISTERS OFFSET AND FULL-SCALE ADJUSTMENT POSITIVE FULL-SCALE ADJUST NEGATIVE FULL-SCALE ADJUST DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS INTERMODULATION DISTORTION AC LINEARITY PLOTS MEASURING APERTURE JITTER MICROPROCESSOR INTERFACING AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 INTERFACE AD7864 TO TMS320C5x INTERFACE AD7864 TO MC68HC000 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7864S IN A SYSTEM OUTLINE DIMENSIONS ORDERING GUIDE