Datasheet AD7864 (Analog Devices) - 6

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AD7864 TIMING CHARACTERISTICS
VDRIVE = 5 V± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 2. Parameter A, B Versions Unit Test Conditions/Comments
tCONV 1.65 μs max Conversion time, internal clock 13 Clock cycles Conversion time, external clock 2.6 μs max CLKIN = 5 MHz tACQ 0.34 μs max Acquisition time tBUSY No. of channels × μs max Selected number of channels multiplied by (tCONV + EOC pulse (tCONV + t9) − t9 width)—EOC pulse width tWAKE-UP —External VREF 2 μs max STBY rising edge to CONVST rising edge t 3 WAKE-UP —Internal VREF 6 ms max STBY rising edge to CONVST rising edge t1 35 ns min CONVST pulse width t2 70 ns max CONVST rising edge to BUSY rising edge READ OPERATION t3 0 ns min CS to RD setup time t4 0 ns min CS to RD hold time t5 35 ns min Read pulse width, VDRIVE = 5 V 40 ns min Read pulse width, VDRIVE = 3 V t 4 6 35 ns max Data access time after falling edge of RD, VDRIVE = 5 V 40 ns max Data access time after falling edge of RD, VDRIVE = 3 V t 5 7 5 ns min Bus relinquish time after rising edge of RD 30 ns max t8 10 ns min Time between consecutive reads t9 75 ns min EOC pulse width 180 ns max t10 70 ns max RD rising edge to FRSTDATA edge (rising or falling) t11 15 ns max EOC falling edge to FRSTDATA falling delay t12 0 ns min EOC to RD delay WRITE OPERATION t13 20 ns min WR pulse width t14 0 ns min CS to WR setup time t15 0 ns min WR to CS hold time t16 5 ns min Input data setup time of rising edge of WR t17 5 ns min Input data hold time 1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 9, Figure 10,and Figure 11. 3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the VREF pin. 4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part, and as such, are independent of external bus loading capacitances.
1.6mA TO OUTPUT 1.6V 50pF 400µA
02 0 1- 34 01 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. D | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Reference CIRCUIT DESCRIPTION ANALOG INPUT AD7864-1 AD7864-2 AD7864-3 SELECTING A CONVERSION SEQUENCE TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence Reading After the Conversion Sequence USING AN EXTERNAL CLOCK STANDBY MODE OPERATION ACCESSING THE OUTPUT DATA REGISTERS OFFSET AND FULL-SCALE ADJUSTMENT POSITIVE FULL-SCALE ADJUST NEGATIVE FULL-SCALE ADJUST DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS INTERMODULATION DISTORTION AC LINEARITY PLOTS MEASURING APERTURE JITTER MICROPROCESSOR INTERFACING AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 INTERFACE AD7864 TO TMS320C5x INTERFACE AD7864 TO MC68HC000 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7864S IN A SYSTEM OUTLINE DIMENSIONS ORDERING GUIDE