Datasheet AD9201 (Analog Devices) - 4

HerstellerAnalog Devices
BeschreibungDual Channel 20 MHz 10-Bit Resolution CMOS ADC
Seiten / Seite21 / 4 — AD9201. Parameter. Symbol. Min. Typ. Max. Units. Condition. tOD. CLOCK. …
RevisionD
Dateiformat / GrößePDF / 473 Kb
DokumentenspracheEnglisch

AD9201. Parameter. Symbol. Min. Typ. Max. Units. Condition. tOD. CLOCK. INPUT. ADC SAMPLE. SELECT. Q CHANNEL. I CHANNEL. OUTPUT ENABLED. SAMPLE #1-1

AD9201 Parameter Symbol Min Typ Max Units Condition tOD CLOCK INPUT ADC SAMPLE SELECT Q CHANNEL I CHANNEL OUTPUT ENABLED SAMPLE #1-1

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AD9201 Parameter Symbol Min Typ Max Units Condition
DYNAMIC PERFORMANCE (SE)3 Signal-to-Noise and Distortion SINAD f = 3.58 MHz 52.3 dB Signal-to-Noise SNR f = 3.58 MHz 55.5 dB Total Harmonic Distortion THD f = 3.58 MHz –55 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –58 dB DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DC Leakage Current I ± IN 6 µA Input Capacitance CIN 2 pF LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH 2.88 V Low Level Output Voltage (IOL = 1.5 mA) VOL 0.095 V LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH 4.5 V Low Level Output Voltage (IOL = 1.5 mA) VOL 0.4 V Data Valid Delay tOD 11 ns MUX Select Delay tMD 7 ns Data Enable Delay tED 13 ns CL = 20 pF. Output Level to 90% of Final Value Data High-Z Delay tDHZ 13 ns CLOCKING Clock Pulsewidth High tCH 22.5 ns Clock Pulsewidth Low tCL 22.5 ns Pipeline Latency 3.0 Cycles NOTES 1AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V. 2IMD referred to larger of two input signals. 3SE is single ended input, REFT = 1.5 V, REFB = –0.5 V. Specifications subject to change without notice.
tOD CLOCK INPUT ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE #1 #2 #3 #4 #5 SELECT Q CHANNEL t I CHANNEL MD INPUT OUTPUT ENABLED OUTPUT ENABLED SAMPLE #1-1 SAMPLE #1 SAMPLE #2 Q CHANNEL Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-3 SAMPLE #1-2 DATA Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-1 SAMPLE #1 I CHANNEL I CHANNEL OUTPUT OUTPUT
Figure 1. ADC Timing REV. D –3–