Datasheet AD9281 (Analog Devices) - 10

AD9281
The AD9281 can accommodate a variety of input spans be-
1.5V
tween 1 V and 2 V. For spans of less than 1 V, expect a propor-
0.1
m
F 0.5V I OR QREFT
tionate degradation in SNR. Use of a 2 V span will provide the
ANALOG IINA 0.1
m
F 10
m
F INPUT
best noise performance. 1 V spans will provide lower distortion
1k
V
I OR QREFB
when using a 3 V analog supply. Users wishing to run with larger
IINB 0.1
m
F
full-scales are encouraged to use a 5 V analog supply (AVDD).
1.0
m
F 0.1
m
F AD9281 Single-Ended Inputs:
For single-ended input signals, the
VREF REFSENSE
signal is applied to one input pin and the other input pin is tied to a midscale voltage. This midscale voltage defines the center of the full-scale span for the input signal. Figure 18. Example Configuration for 0.5 V–1.5 V ac Coupled Single-Ended Inputs EXAMPLE: For a single-ended input range from 0 V to 1 V applied to IINA, we would configure the converter for a 1 V
Transformer Coupled Inputs
reference (see Figure 17) and apply 0.5 V to IINB. Another option for input ac coupling is to use a transformer. This not only provides dc rejection, but also allows truly differ-
1V
ential drive of the AD9281’s analog inputs, which will provide the optimal distortion performance. Figure 19 shows a recom-
0V 0.1
m
F
mended transformer input drive configuration. Resistors R1 and
INPUT IINA I OR QREFT
R2 define the termination impedance of the transformer cou-
0.1
m
F 10
m
F MIDSCALE VOLTAGE
pling. The center tap of the transformer secondary is tied to the
IINB I OR QREFB = 0.5V (1V) 10
m
F
common-mode voltage, establishing the dc bias point for the
0.1
m
F 0.1
m
F AD9281
analog inputs.
5k
V
5k
V
VREF REF SENSE IINA QINA R1 R2 0.1
m
F 10
m
F IINB QINB COMMON AD9281 0.1
m
F
Figure 17. Example Configuration for 0 V–1 V Single-
MODE I OR QREFT
Ended Input Signal
VOLTAGE 0.1
m
F 10
m
F VREF
Note that since the inputs are high impedance, this reference
10
m
F 0.1
m
F I OR QREFB 0.1
m
F
level can easily be generated with an external resistive divider
REFSENSE
with large resistance values (to minimize power dissipation). A decoupling capacitor is recommended on this input to minimize Figure 19. Example Configuration for Transformer the high frequency noise-coupling onto this pin. Decoupling Coupled Inputs should occur close to the ADC.
Crosstalk:
The internal layout of the AD9281, as well as its
Differential Inputs
pinout, was configured to minimize the crosstalk between the Use of differential input signals can provide greater flexibility in two input signals. Users wishing to minimize high frequency input ranges and bias points, as well as offering improvements in crosstalk should take care to provide the best possible decoupling distortion performance, particularly for high frequency input for input pins (see Figure 20). R and C values will make a pole signals. Users with differential input signals will probably want dependant on antialiasing requirements. Decoupling is also to take advantage of the differential input structure of the AD9281. required on reference pins and power supplies (see Figure 21). Performance is still very good for single-ended inputs. Convert- ing a single-ended input to a differential signal for application to the converter is probably only worth considering for very high
IINA QINA
frequency input signals.
AD9281 AC-Coupled Inputs IINB QINB
If the signal of interest has no dc component, ac coupling can be easily used to define an optimum bias point. Figure 18 illustrates Figure 20. Input Loading one recommended configuration. The voltage chosen for the dc bias point (in this case the 1 V reference) is applied to both
V ANALOG V DIGITAL
IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA is coupled to the input signal through Capacitor C1, while IINB is
AVDD DVDD
decoupled to ground through Capacitor C2.
10
m
F 0.1
m
F 0.1
m
F 10
m
F AD9281 I OR QREFT 0.1
m
F 10
m
F 0.1
m
F I OR QREFB 0.1
m
F
Figure 21. Reference and Power Supply Decoupling REV. F –9–