Datasheet AD9281 (Analog Devices) - 5

AD9281 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS With Pin Respect No. Name Description Parameter to Min Max Units
1 DVSS Digital Ground AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V 2 DVDD Digital Supply AVSS DVSS –0.3 +0.3 V 3 DNC Do not connect AVDD DVDD –6.5 +6.5 V 4 DNC Do not connect CLK AVSS –0.3 AVDD + 0.3 V 5 D0 Bit 0 (LSB) Digital Outputs DVSS –0.3 DVDD + 0.3 V 6 D1 Bit 1 AINA, AINB AVSS –1.0 AVDD + 0.3 V 7 D2 Bit 2 VREF AVSS –0.3 AVDD + 0.3 V REFSENSE AVSS –0.3 AVDD + 0.3 V 8 D3 Bit 3 REFT, REFB AVSS –0.3 AVDD + 0.3 V 9 D4 Bit 4 Junction Temperature +150 °C 10 D5 Bit 5 Storage Temperature –65 +150 °C 11 D6 Bit 6 Lead Temperature 12 D7 Bit 7 (MSB) 10 sec +300 °C 13 SELECT Hi I Channel Out, Lo Q Channel Out *Stresses above those listed under Absolute Maximum Ratings may cause perma- 14 CLOCK Clock nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 15 SLEEP Hi Power Down, Lo Normal Operation sections of this specification is not implied. Exposure to absolute maximum ratings 16 INA-I I Channel, A Input for extended periods may effect device reliability. 17 INB-I I Channel, B Input 18 REFT-I Top Reference Decoupling, I Channel 19 REFB-I Bottom Reference Decoupling, I Channel 20 AVSS Analog Ground 21 REFSENSE Reference Select 22 VREF Internal Reference Output 23 AVDD Analog Supply 24 REFB-Q Bottom Reference Decoupling, Q Channel 25 REFT-Q Top Reference Decoupling, Q Channel
PIN CONFIGURATION
26 INB-Q Q Channel B Input 27 INA-Q Q Channel A Input
DVSS CHIP-SELECT
28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation
DVDD INA-Q
DNC
INB-Q
DNC
REFT-Q DEFINITIONS OF SPECIFICATIONS (LSB) D0 AD9281 REFB-Q INTEGRAL NONLINEARITY (INL) D1 TOP VIEW AVDD (Not to Scale)
Integral nonlinearity refers to the deviation of each individual
D2 VREF
code from a line drawn from “zero” through “full scale.” The
D3 REFSENSE
point used as “zero” occurs 1/2 LSB before the first code transi-
D4 AVSS
tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last
D5 REFB-I
code transition. The deviation is measured from the center of
D6 REFT-I
each particular code to the true straight line.
(MSB) D7 INB-I SELECT INA-I DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CLOCK SLEEP CODES) NC = NO CONNECT
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD9281 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. F