Datasheet AD7723 (Analog Devices) - 10

AD7723 t18 CLKIN t t 19 19 t17 DRDY t20 DB0–DB15 WORD N – 1 WORD N WORD N + 1
01186-008 Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low
CLKIN t18 t19 DRDY t t 22 19 RD/CS t 21 t22 t21 t24 DB0–DB15 VALID DATA
01186-009
t23
Figure 9. Parallel Mode Read Timing, CS = RD
t28 CLKIN t26 SYNC t25 DRDY t
01186-010
27
Figure 10. SYNC Timing Rev. C | Page 9 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT DRIVING THE ANALOG INPUTS APPLYING THE REFERENCE CLOCK GENERATION SYSTEM SYNCHRONIZATION DATA INTERFACING PARALLEL INTERFACE SERIAL INTERFACE TWO-CHANNEL MULTIPLEXED OPERATION SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE AD7723 TO SHARC INTERFACE AD7723 TO DSP56002 INTERFACE AD7723 TO TMS320C5x INTERFACE GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE