Datasheet AD7856 (Analog Devices) - 6

AD7856 TYPICAL TIMING DIAGRAMS 1.6mA IOL
Figures 2 and 3 show typical read and write timing diagrams for serial Interface Mode 2. The reading and writing occurs after
TO OUTPUT
conversion in Figure 2, and during conversion in Figure 3. To
+2.1V PIN CL
attain the maximum sample rate of 285 kHz, reading and writ-
100pF
ing must be performed during conversion as in Figure 3. At
200
m
A I
least 330 ns acquisition time must be allowed (the time from
OL
the falling edge of BUSY to the next rising edge of CONVST) Figure 1. Load Circuit for Digital Output Timing before the next conversion begins to ensure that the part is Specifications settled to the 14-bit level. If the user does not want to provide the CONVST signal, the conversion can be initiated in software by writing to the control register.
tCONVERT = 3.5
m
s MAX, 5.25
m
s MAX FOR K VERSION t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t t 3 11 t9 SCLK (I/P) 1 5 6 16 t4 t10 t t 6 t6 12 THREE- THREE-STATE STATE DOUT (O/P) DB15 DB11 DB0 t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
tCONVERT = 3.5
m
s MAX, 5.25
m
s MAX FOR K VERSION t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t t 3 11 t9 SCLK (I/P) 1 5 6 16 t4 t10 t t 12 6 t6 THREE- THREE-STATE STATE DOUT (O/P) DB15 DB11 DB0 t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion) REV. A –5–