Datasheet AD7888 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 2.7 V to 5.25 V, Micro Power, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Pin TSSOP |
| Seiten / Seite | 18 / 8 — AD7888. CONTROL REGISTER. Table I. Control Register Bit Function … |
| Revision | C |
| Dateiformat / Größe | PDF / 246 Kb |
| Dokumentensprache | Englisch |
AD7888. CONTROL REGISTER. Table I. Control Register Bit Function Description. MSB. R F. Bit. Mnemonic. Comment. PERFORMANCE CURVES. 73.0
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AD7888 CONTROL REGISTER
The Control Register on the AD7888 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7888 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer. Only the information provided on the first 8 rising clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The default contents of the Control Register on power-up is all zeros.
Table I. Control Register Bit Function Description MSB C T N O D O R E Z 2 D D A 1 D D A 0 D D A E R F M P 1 0 M P Bit Mnemonic Comment
7 DONTC Don’t Care. The value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if the bit is 0 or 1. 6 ZERO A zero must be written to this bit to ensure correct operation of the AD7888. 5 ADD2 These three address bits are loaded at the end of the present conversion sequence and select which analog input 4 ADD1 channel is converted for the next conversion. The selected input channel is decoded as shown in Table II. 3 ADD0 2 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is disabled. To obtain best performance from the AD7888, the internal reference should be disabled when using an externally applied reference source. (See On-Chip Reference section.) 1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7888 as shown in Table III.
PERFORMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7888 at 100 kHz Figure 3 shows a typical plot for the SNR vs. frequency for a sample rate and 10 kHz input frequency. 5 V supply and with a 5 V external reference.
73.0 –10 4096 POINT FFT SAMPLING VDD = 5V 100kSPS 5V EXT REFERENCE fIN = 10kHz 72.5 –30 SNR = 70dB –50 dB – dB 72.0 SNR –70 71.5 –90 –110 71.0 0 12.21 24.41 36.62 48.83 0 10.89 21.14 31.59 42.14 FREQUENCY – kHz INPUT FREQUENCY – kHz
Figure 2. Dynamic Performance Figure 3. SNR vs. Input Frequency REV. C –7–
The Control Register on the AD7888 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7888 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer. Only the information provided on the first 8 rising clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The default contents of the Control Register on power-up is all zeros.
Table I. Control Register Bit Function Description MSB C T N O D O R E Z 2 D D A 1 D D A 0 D D A E R F M P 1 0 M P Bit Mnemonic Comment
7 DONTC Don’t Care. The value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if the bit is 0 or 1. 6 ZERO A zero must be written to this bit to ensure correct operation of the AD7888. 5 ADD2 These three address bits are loaded at the end of the present conversion sequence and select which analog input 4 ADD1 channel is converted for the next conversion. The selected input channel is decoded as shown in Table II. 3 ADD0 2 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is disabled. To obtain best performance from the AD7888, the internal reference should be disabled when using an externally applied reference source. (See On-Chip Reference section.) 1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7888 as shown in Table III.
PERFORMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7888 at 100 kHz Figure 3 shows a typical plot for the SNR vs. frequency for a sample rate and 10 kHz input frequency. 5 V supply and with a 5 V external reference.
73.0 –10 4096 POINT FFT SAMPLING VDD = 5V 100kSPS 5V EXT REFERENCE fIN = 10kHz 72.5 –30 SNR = 70dB –50 dB – dB 72.0 SNR –70 71.5 –90 –110 71.0 0 12.21 24.41 36.62 48.83 0 10.89 21.14 31.59 42.14 FREQUENCY – kHz INPUT FREQUENCY – kHz
Figure 2. Dynamic Performance Figure 3. SNR vs. Input Frequency REV. C –7–