Datasheet AD7470, AD7472 (Analog Devices) - 5

AD7470/AD7472 TIMING SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX Parameter AD7470 AD7472 Unit Description
f 2 CLK 10 10 kHz min 30 26 MHz max tCONVERT 436.42 531.66 ns min tCLK = 1/fCLK IN tWAKEUP 1 1 µs max Wake-Up Time t1 10 10 ns min CONVST Pulse Width t CONVST 2 to BUSY Delay, 10 10 ns max VDD = 5 V, A and B Versions 15 ns max VDD = 5 V, Y Version 30 30 ns max VDD = 3 V, A and B Versions 35 ns max VDD = 3 V, Y Version t3 0 0 ns max BUSY to CS Setup Time t 3 4 0 0 ns max CS to RD Setup Time t5 20 20 ns min RD Pulse Width t 3 6 15 15 ns min Data Access Time After Falling Edge of RD t 4 7 8 8 ns max Bus Relinquish Time After Rising Edge of RD t8 0 0 ns max CS to RD Hold Time t9 Acquisition Time 135 135 ns max A and B Versions 140 ns max Y Version t10 100 100 ns min Quiet Time NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Figure 1. 2Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
200
␮
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
␮
A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications REV. B –5– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track-and-Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Aperture Delay Aperture Jitter CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME Reference Input DC ACQUISITION TIME ANALOG INPUT CLOCK SOURCES PARALLEL INTERFACE OPERATING MODES Mode 1 (High Speed Sampling) Mode 2 (Sleep Mode) Burst Mode VDRIVE POWER-UP Power vs. Throughput Mode 1 Mode 2 Typical Performance Characteristics GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING AD7470/AD7472 to ADSP-2185 Interface AD7470/AD7472 to ADSP-21065 Interface AD7470/AD7472 to TMS320C25 Interface AD7470/AD7472 to PIC17C4x Interface AD7470/AD7472 to 80C186 Interface OUTLINE DIMENSIONS Revision History