Datasheet AD7707 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| Seiten / Seite | 53 / 6 — AD7707. Parameter. B Version1 Unit. Conditions/Comments |
| Revision | B |
| Dateiformat / Größe | PDF / 788 Kb |
| Dokumentensprache | Englisch |
AD7707. Parameter. B Version1 Unit. Conditions/Comments
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 8 link to page 8 link to page 53 link to page 8 link to page 8 link to page 8 link to page 53 link to page 53 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8 link to page 8
AD7707 Parameter B Version1 Unit Conditions/Comments
Common-Mode 60 Hz Rejection2 150 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × fNOTCH Absolute/Common-Mode REF IN Voltage2 AGND to AVDD V min to V max Absolute/Common-Mode AIN Voltage2, 10 AGND – 100 mV V min BUF bit of setup register = 0 AVDD + 30 mV V max AGND + 50 mV V min BUF bit of setup register = 1 AVDD − 1.5 V V max AIN DC Input Current2 1 nA max AIN Sampling Capacitance2 10 pF max BUF = 0 AIN Differential Voltage Range11, 12 0 to +VREF/gain V nom Unipolar input range (B/U bit of setup register = 1) ±VREF/gain V nom Bipolar input range (B/U bit of setup register = 0) AIN Input Sampling Rate, fS Gain × fCLKIN/64 Hz nom For gains of 1 to 4 fCLKIN/8 For gains of 8 to 128 Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/max AVDD = 2.7 V to 3.3 V; VREF = 1.225 V ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/max AVDD = 4.75 V to 5.25 V; VREF = 2.5 V ± 1% for specified performance REF IN Input Sampling Rate, fS fCLKIN/64 ±100 mV INPUT RANGE Low level input channels, AIN1 and AIN2; gain = 16, unbuffered mode INL2 ±0.003 % of FSR max Filter notch < 60 Hz Input Common-Mode Rejection (CMR)2 80 dB typ Power Supply Rejection (PSR)2 90 dB typ HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 is with respect to HICOM AIN3 Voltage Range +10 V max −10 V min Normal Mode 50 Hz Rejection 78 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Normal Mode 60 Hz Rejection 78 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH AIN3 Input Sampling Rate, fS Gain × fCLKIN/64 Hz nom For gains of 1 to 4 fCLKIN/8 Hz nom For gains of 8 to 128 AIN3 Input Impedance2 27 kΩ min Typically 30 kΩ ± 10%; typical resistor Tempco is −30 ppm/°C AIN3 Sampling Capacitance2 10 pF max VBIAS Input Range 0 V/AVDD V min/max Typically REFIN(+) = 2.5 V LOGIC INPUTS Input Current All Inputs Except MCLK IN ±1 μA max Typically ±20 nA MCLK ±10 μA max Typically ±2 m A All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V max DVDD = 3 V and 5 V SCLK Only (Schmitt Triggered Input) DVDD = 5 V nominal VT+ 1.4/3 V min/V max VT− 0.8/1.4 V min/V max VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt Triggered Input) DVDD = 3 V nominal VT+ 1/2.5 V min/V max VT− 0.4/1.1 V min/V max VT+ − VT− 0.375/0.8 V min /V max Rev. B | Page 5 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
AD7707 Parameter B Version1 Unit Conditions/Comments
Common-Mode 60 Hz Rejection2 150 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × fNOTCH Absolute/Common-Mode REF IN Voltage2 AGND to AVDD V min to V max Absolute/Common-Mode AIN Voltage2, 10 AGND – 100 mV V min BUF bit of setup register = 0 AVDD + 30 mV V max AGND + 50 mV V min BUF bit of setup register = 1 AVDD − 1.5 V V max AIN DC Input Current2 1 nA max AIN Sampling Capacitance2 10 pF max BUF = 0 AIN Differential Voltage Range11, 12 0 to +VREF/gain V nom Unipolar input range (B/U bit of setup register = 1) ±VREF/gain V nom Bipolar input range (B/U bit of setup register = 0) AIN Input Sampling Rate, fS Gain × fCLKIN/64 Hz nom For gains of 1 to 4 fCLKIN/8 For gains of 8 to 128 Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/max AVDD = 2.7 V to 3.3 V; VREF = 1.225 V ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/max AVDD = 4.75 V to 5.25 V; VREF = 2.5 V ± 1% for specified performance REF IN Input Sampling Rate, fS fCLKIN/64 ±100 mV INPUT RANGE Low level input channels, AIN1 and AIN2; gain = 16, unbuffered mode INL2 ±0.003 % of FSR max Filter notch < 60 Hz Input Common-Mode Rejection (CMR)2 80 dB typ Power Supply Rejection (PSR)2 90 dB typ HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 is with respect to HICOM AIN3 Voltage Range +10 V max −10 V min Normal Mode 50 Hz Rejection 78 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Normal Mode 60 Hz Rejection 78 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH AIN3 Input Sampling Rate, fS Gain × fCLKIN/64 Hz nom For gains of 1 to 4 fCLKIN/8 Hz nom For gains of 8 to 128 AIN3 Input Impedance2 27 kΩ min Typically 30 kΩ ± 10%; typical resistor Tempco is −30 ppm/°C AIN3 Sampling Capacitance2 10 pF max VBIAS Input Range 0 V/AVDD V min/max Typically REFIN(+) = 2.5 V LOGIC INPUTS Input Current All Inputs Except MCLK IN ±1 μA max Typically ±20 nA MCLK ±10 μA max Typically ±2 m A All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V max DVDD = 3 V and 5 V SCLK Only (Schmitt Triggered Input) DVDD = 5 V nominal VT+ 1.4/3 V min/V max VT− 0.8/1.4 V min/V max VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt Triggered Input) DVDD = 3 V nominal VT+ 1/2.5 V min/V max VT− 0.4/1.1 V min/V max VT+ − VT− 0.375/0.8 V min /V max Rev. B | Page 5 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE