Datasheet AD1555, AD1556 (Analog Devices) - 5

AD1555/AD1556 (+V TIMING SPECIFICATIONS A = +5 V 5%; –VA = –5 V 5%; AD1555 VL = 5 V 5%, AD1556 VL = 2.85 V to 5.25 V; CLKIN = 1.024 MHz; AGND = DGND = 0 V; CL = 50 pF; TA = TMIN to TMAX, unless otherwise noted) Symbol Min Typ Max Unit
CLKIN Frequency1 fCLKIN 0.975 1.024 1.075 MHz CLKIN Duty Cycle Error 45 55 % MCLK Output Frequency1 fCLKIN/4 SYNC Setup Time t1 10 ns SYNC Hold Time t2 10 ns CLKIN Rising to MCLK Output Falling on SYNC t3 20 ns CLKIN Falling to MCLK Output Rising t4 20 ns CLKIN Falling to MCLK Output Falling t5 20 ns MCLK Input Falling to MDATA Falling t6 30 ns MCLK Input Rising to MDATA and MFLG Valid t7 100 ns TDATA Setup Time after SYNC t8 5 ns TDATA Hold Time t9 5 ns RESET Setup Time t10 15 ns RESET Hold Time t11 15 ns CLKIN Falling to DRDY Rising t12 20 ns CLKIN Rising to DRDY Falling2 t13 20 ns CLKIN Rising to ERROR Falling t14 50 ns RSEL to Data Valid t15 25 ns RSEL Setup to SCLK Falling t16 10 ns DRDY to Data Valid t17 25 ns DRDY High Setup to SCLK Falling t18 10 ns R/W to Data Valid t19 25 ns R/W High Setup to SCLK Falling t20 10 ns CS to Data Valid t21 25 ns CS Low Setup to SCLK Falling t22 10 ns SCLK Rising to DOUT Valid t23 25 ns SCLK High Pulsewidth t24 25 ns SCLK Low Pulsewidth t25 25 ns SCLK Period t26 70 ns SCLK Falling to DRDY Falling2 t27 20 ns CS High or R/W Low to DOUT Hi-Z t28 20 ns R/W Low Setup to SCLK Falling t29 10 ns CS Low Setup to SCLK Falling t30 10 ns Data Setup Time to SCLK Falling t31 10 ns Data Hold Time after SCLK Falling t32 10 ns R/W Hold Time after SCLK Falling t33 10 ns NOTES 1The gain of the modulator is proportional to fCLKIN and MCLK frequency. 2With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor. Specifications subject to change without notice.
1.6mA IOL TO OUTPUT 1.4V PIN CL 50pF 500 A IOH
Figure 2. Load Circuit for Digital Interface Timing REV. B –5–