Datasheet AD7898 (Analog Devices) - 8

Typical Performance Characteristics–AD7898 PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7898 at 220 kSPS sampling rate with a 30 kHz input frequency while operating in Mode 0.
5 –20 8192 POINT FFT fSAMPLE = 220kSPS –15 f –30 IN = 30kHz SINAD = 71.823dB THD = –90.28dB –35 SFDR = –91.467dB –40 –55 –50 SNR – dB PSRR – dB –75 –60 –95 –70 –115 –80 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 FREQUENCY – kHz INPUT FREQUENCY – kHz
TPC 1. Mode 0 Dynamic Performance TPC 3. PSRR vs. Supply Ripple Frequency TPC 2 shows a typical FFT plot for the AD7898 at 220 kSPS TPC 4 shows a graph of effective number of bits versus input sampling rate with a 30 kHz input frequency while operating in frequency while sampling at 220 kSPS. Mode 1.
5 11.9 8192 POINT FFT fSAMPLE = 220kSPS 11.8 –15 fIN = 30kHz SINAD = 71.779dB THD = –88.337dB 11.7 –35 SFDR = –89.639dB 11.6 –55 SNR – dB 11.5 –75 11.4 EFFECTIVE NUMBER OF BITS –95 11.3 –115 11.2 0 20 40 60 80 100 0 20 40 60 80 100 FREQUENCY – kHz INPUT FREQUENCY – kHz
TPC 2. Mode 1 Dynamic Performance TPC 4. Effective Number of Bits vs. Input Frequency at 220 kSPS TPC 3 shows the Power Supply Rejection Ratio versus supply frequency for the AD7898. The power supply rejection ratio is The effective number of bits for a device can be calculated from defined as the ratio of the power in the ADC output at full-scale its measured Signal to (Noise + Distortion) Ratio (see Termi- frequency f, to the power of a 100 mV sine wave applied to the nology section). TPC 4 shows a typical plot of effective number ADC V of bits versus frequency for the AD7898 from dc to f DD supply of frequency fS. SAMPLE/2. The sampling frequency is 220 kSPS. PSRR (dB) = 10 log (Pf/Pfs) The formula for Signal to (Noise + Distortion) Ratio is related Pf = Power at frequency f in ADC output, Pfs = power at fre- to the resolution or number of bits in the converter. Rewriting quency fs coupled on to the ADC VDD supply input. Here a the formula, below, gives a measure of performance expressed in 100 mV peak-to-peak sine wave is coupled onto the VDD supply. effective number of bits (N): 100 nF decoupling was used on the supply. N = (SNR – 1.76)/6.02 where SNR is Signal to (Noise + Distortion) Ratio. REV. A –7– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7898-10) Positive Full-Scale Error (AD7898-3) Bipolar Zero Error (AD7898-10, AD7898-3) Negative Full-Scale Error (AD7898-10) Negative Full-Scale Error (AD7898-3) Track/Hold Acquisition Time PSR (Power Supply Rejection) PERFORMANCE CURVES Noise CONVERTER DETAILS CIRCUIT DESCRIPTION Analog Input Section Acquisition Time TYPICAL CONNECTION DIAGRAM VDRIVE Feature Track/Hold Section Reference Input SERIAL INTERFACE OPERATING MODES Mode 0 Operation Mode 1 Operation Mode Selection Power-Down Mode Power-Up Times MICROPROCESSOR/MICROCONTROLLER INTERFACE FOR MODE 0 OPERATION 8x51/L51 to AD7898 Interface 68HC11/L11 to AD7898 Interface ADSP-2103/ADSP-2105 to AD7898 Interface DSP56002/L002 to AD7898 Interface MICROPROCESSOR INTERFACING FOR MODE 1 TMS320C5x/C54x to AD7898 Interface AD7898 to ADSP-21xx Interface AD7898 to DSP56xxx Interface AD7898 to MC68HC16 Interface OUTLINE DIMENSIONS Revision History