Datasheet AD7475, AD7495 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8 |
| Seiten / Seite | 24 / 8 — AD7475/AD7495. Data Sheet. TIMING EXAMPLE 1. TIMING EXAMPLE 2. tCONVERT. … |
| Revision | D |
| Dateiformat / Größe | PDF / 436 Kb |
| Dokumentensprache | Englisch |
AD7475/AD7495. Data Sheet. TIMING EXAMPLE 1. TIMING EXAMPLE 2. tCONVERT. SCLK. QUIET. SDATA. DB11. DB10. DB2. DB1. DB0. THREE-STATE
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AD7475/AD7495 Data Sheet TIMING EXAMPLE 1 TIMING EXAMPLE 2
With f With f SCLK = 20 MHz and a throughput of 1 MSPS, the cycle SCLK = 5 MHz and a throughput of 315 KSPS, the cycle time is t time is t 2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, tACQ 2 + 12.5(1/fSCLK) + tACQ = 3.174 µs. With t2 = 10 ns min, is 365 ns. The 365 ns satisfies the requirement of 300 ns for t t ACQ. ACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for In Figure 3, t t ACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. ACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where This allows a value of 195 ns for t t8 = 45 ns. This allows a value of 119 ns for t QUIET, satisfying the minimum QUIET, satisfying the requirement of 100 ns. minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2, the signal is acquired at approximately Point C in Figure 3.
CS tCONVERT t t 2 6 B SCLK 1 2 3 4 5 13 14 15 16 t t 5 7 t t 8 QUIET t t 3 4 SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE FOUR LEADING ZEROS
01684-B-002 Figure 2. Serial Interface Timing Diagram
CS tCONVERT t t 2 6 B C SCLK 1 2 3 4 5 13 14 15 16 t5 t8 tQUIET 45ns 12.5 (1/fSCLK) tACQUISITION 10ns 1/THROUGHPUT
01684-B-003 Figure 3. Serial Interface Timing Example
200
µ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
µ
A IOH
01684-B-004 Figure 4. Load Circuit for Digital Output Timing Specifications Rev. C | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY AD7475 SPECIFICATIONS AD7495 SPECIFICATIONS TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs VDRIVE Reference Section OPERATING MODES NORMAL MODE PARTIAL POWER-DOWN MODE Power-Up Time FULL POWER-DOWN MODE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7475/AD7495 TO TMS320C5x/C54x AD7475/AD7495 TO ADSP-21xx AD7475/AD7495 TO DSP56xxx AD7475/AD7495 TO MC68HC16 OUTLINE DIMENSIONS ORDERING GUIDE
AD7475/AD7495 Data Sheet TIMING EXAMPLE 1 TIMING EXAMPLE 2
With f With f SCLK = 20 MHz and a throughput of 1 MSPS, the cycle SCLK = 5 MHz and a throughput of 315 KSPS, the cycle time is t time is t 2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, tACQ 2 + 12.5(1/fSCLK) + tACQ = 3.174 µs. With t2 = 10 ns min, is 365 ns. The 365 ns satisfies the requirement of 300 ns for t t ACQ. ACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for In Figure 3, t t ACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. ACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where This allows a value of 195 ns for t t8 = 45 ns. This allows a value of 119 ns for t QUIET, satisfying the minimum QUIET, satisfying the requirement of 100 ns. minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2, the signal is acquired at approximately Point C in Figure 3.
CS tCONVERT t t 2 6 B SCLK 1 2 3 4 5 13 14 15 16 t t 5 7 t t 8 QUIET t t 3 4 SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE FOUR LEADING ZEROS
01684-B-002 Figure 2. Serial Interface Timing Diagram
CS tCONVERT t t 2 6 B C SCLK 1 2 3 4 5 13 14 15 16 t5 t8 tQUIET 45ns 12.5 (1/fSCLK) tACQUISITION 10ns 1/THROUGHPUT
01684-B-003 Figure 3. Serial Interface Timing Example
200
µ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
µ
A IOH
01684-B-004 Figure 4. Load Circuit for Digital Output Timing Specifications Rev. C | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY AD7475 SPECIFICATIONS AD7495 SPECIFICATIONS TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs VDRIVE Reference Section OPERATING MODES NORMAL MODE PARTIAL POWER-DOWN MODE Power-Up Time FULL POWER-DOWN MODE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7475/AD7495 TO TMS320C5x/C54x AD7475/AD7495 TO ADSP-21xx AD7475/AD7495 TO DSP56xxx AD7475/AD7495 TO MC68HC16 OUTLINE DIMENSIONS ORDERING GUIDE