Datasheet AD7671 (Analog Devices) - 6

AD7671 ABSOLUTE MAXIMUM RATINGS1 PIN CONFIGURATION
Analog Inputs
ST-48 and CP-48
-1 IND2, INC2, INB2 . –11 V to +30 V INA, REF, INGND, REFGND, AGND . – 0.3 V to AVDD + 0.3 V Ground Voltage Differences
NC NC NC NC NC IND(4R) INC(4R) INB(2R) INA(R) INGND REFGND REF
AGND, DGND, OGND . .
48
±0.3 V
47 46 45 44 43 42 41 40 39 38 37
Supply Voltages
AGND 1 36 AGND PIN 1
AVDD, DVDD, OVDD . –0.3 V to +7 V
AVDD 2 IDENTIFIER 35 CNVST
AVDD to DVDD,
NC 3 34 PD
AVDD to OVDD . ± 7 V
BYTESWAP 4 33 RESET
DVDD to OVDD . –0.3 V to +7 V
OB/2C 5 32 CS
Digital Inputs . –0.3 V to DVDD + 0.3 V
WARP AD7671 6 31 RD
Internal Power Dissipation3 . 700 mW
TOP VIEW IMPULSE 7 30 (Not to Scale) DGND
Internal Power Dissipation4 . 2.5 W
SER/PAR 8 29 BUSY
Junction Temperature . 150
D0 9
∞C
28 D15 D1 10 27 D14
Storage Temperature Range . –65∞C to +150∞C
D2/DIVSCLK[0] 11 26 D13
Lead Temperature Range
D3/DIVSCLK[1] 12 25 D12
(Soldering 10 sec) . 300∞C
13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT
NOTES
D D
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
INT D D OR
damage to the device. This is a stress rating only; functional operation of the device
OGND OV DV DGND D9/SCLK
at these or any other conditions above those indicated in the operational section of
D10/SYNC D4/EXT/ D8/SDOUT
this specification is not implied. Exposure to absolute maximum rating conditions
D5/INVSYNC D6/INVSCLK D7/RDC/SDIN D11/RDERR
for extended periods may affect device reliability. 2 See Analog Inputs section. NOTES: 3 Specification is for device in free air: 48-Lead LQFP: q 1. PADDLE CONNECTED TO AGND FOR THE LFCSP (CP-48-1). THIS JA = 91∞C/W, qJC = 30∞C/W. 4 Specification is for device in free air: 48-Lead LFCSP: q CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL JA = 26∞C/W. PERFORMANCES.
1.6mA IOL TO OUTPUT 1.4V PIN CL 60pF* 2V 500 I A OH 0.8V t t DELAY DELAY *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 2V 2V SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C 0.8V 0.8V L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, Figure 2. Voltage Reference Levels for Timing SDOUT, SYNC, SCLK Outputs, CL = 10 pF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PulSAR Selection PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE SLAVE SERIAL INTERFACE External Clock MASTER SERIAL INTERFACE Internal Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7671 Performance OUTLINE DIMENSIONS Revision History