Datasheet AD7675 (Analog Devices) - 5

AD7675 Table I. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t19 25 50 100 200 ns Internal SCLK Period Typical t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns Busy High Width Maximum t28 2 2.5 3.5 5.75 µs
ABSOLUTE MAXIMUM RATINGS1 1.6mA IOL
Analog Inputs IN+2, IN–2, REF, REFGND . AVDD + 0.3 V to AGND – 0.3 V
TO OUTPUT 1.4V
Ground Voltage Differences
PIN CL
AGND, DGND, OGND . ± 0.3 V
60pF1
Supply Voltages
500 A I
AVDD, DVDD, OVDD . –0.3 V to +7 V
OH NOTE
AVDD to DVDD, AVDD to OVDD . ± 7 V
1 IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
DVDD to OVDD . –0.3 V to +7 V
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Digital Inputs . –0.3 V to DVDD + 0.3 V Internal Power Dissipation3 . 700 mW Figure 1. Load Circuit for Digital Interface Timing, SDOUT, Internal Power Dissipation4 . 2.5 W SYNC, SCLK Outputs, CL = 10 pF Junction Temperature . 150° C Storage Temperature Range . –65°C to +150°C
2V
Lead Temperature Range
0.8V
(Soldering 10 sec) . 300°C
tDELAY tDELAY
NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma-
2V 2V
nent damage to the device. This is a stress rating only; functional operation of the
0.8V 0.8V
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating Figure 2. Voltage Reference Levels for Timing conditions for extended periods may affect device reliability. 2See Analog Input section. 3Specification is for device in free air: 48-Lead LQFP: ␪JA = 91°C/W, ␪JC = 30°C/W. 4Specification is for device in free air: LFCSP: ␪JA = 26°C/W
ORDERING GUIDE Package Model Temperature Range Package Description Option
AD7675AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7675ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7675ACP –40°C to +85°C Chip Scale (LFCSP) CP-48 AD7675ACPRL –40°C to +85°C Chip Scale (LFCSP) CP-48 EVAL-AD7675CB1 Evaluation Board EVAL-CONTROL BRD22 Controller Board NOTES 1This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/ demonstration purposes. 2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although
WARNING!
the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality. –4– REV. A Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PulSAR Selection GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS Table I. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) DIFFERENTIAL NONLINEARITY ERROR (DNL) +FULL-SCALE ERROR –FULL-SCALE ERROR BIPOLAR ZERO ERROR SPURIOUS FREE DYNAMIC RANGE (SFDR) EFFECTIVE NUMBER OF BITS (ENOB) TOTAL HARMONIC DISTORTION (THD) SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-(NOISE + DISTORTION) RATIO (S/[N+D]) APERTURE DELAY TRANSIENT RESPONSE Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Single to Differential Driver Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read During Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7675 Performance OUTLINE DIMENSIONS Revision History