Datasheet AD7650 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 570 kSPS, Unipolar CMOS Successive Approximation ADC |
| Seiten / Seite | 21 / 7 — AD7650. PIN CONFIGURATION. 48-Lead LQFP and 48-Lead LFSCP. (ST-48 and … |
| Dateiformat / Größe | PDF / 267 Kb |
| Dokumentensprache | Englisch |
AD7650. PIN CONFIGURATION. 48-Lead LQFP and 48-Lead LFSCP. (ST-48 and CP-48). IN+. REFGND. REF. 48 47 46 45 44 43 42 41 40 39 38 37
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AD7650 PIN CONFIGURATION 48-Lead LQFP and 48-Lead LFSCP (ST-48 and CP-48) – NC NC NC NC NC IN+ NC NC NC IN REFGND REF 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST NC 3 34 PD DGND 4 33 RESET OB/2C 5 32 CS WARP 6 AD7650 31 RD IMPULSE 7 TOP VIEW 30 DGND (Not to Scale) SER/PAR 8 29 BUSY D0 9 28 D15 D1 10 27 D14 D2 11 26 D13 D3 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT D D INT D D OR OGND OV DV DGND D9/SCLK D10/SYNC D4/EXT/ D8/SDOUT D5/INVSYNC D6/INVSCLK D7/RDC/SDIN D11/RDERR PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 40–42, NC No Connect 44–48 4 DGND DI Must be tied to the ground where DVDD is referred. 5 OB/2C DI Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9–12 DATA[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. 13 DATA[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 DATA[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 DATA[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. REV. 0 –6–
1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 40–42, NC No Connect 44–48 4 DGND DI Must be tied to the ground where DVDD is referred. 5 OB/2C DI Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9–12 DATA[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. 13 DATA[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 DATA[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 DATA[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. REV. 0 –6–