Datasheet AD7450 (Analog Devices) - 5

AD7450 TIMING SPECIFICATIONS1, 2 (VDD = 2.7 V to 3.3 V, fSCLK = 15 MHz, fS = 833 kSPS, VREF = 1.25 V; VDD = 4.75 V to 5.25 V, f 3 SCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM = VREF; TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX Parameter 3 V 5 V Unit Description
f 4 SCLK 50 50 kHz min 15 18 MHz max tCONVERT 16 ⫻ tSCLK 16 ⫻ tSCLK tSCLK = 1/fSCLK 1.07 0.88 µs max SCLK = 15 MHz, 18 MHz tQUIET 25 25 ns min Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS t1 10 10 ns min Minimum CS Pulsewidth t2 10 10 ns min CS Falling Edge to SCLK Falling Edge Setup Time t 5 3 20 20 ns max Delay from CS Falling Edge until SDATA Three-State Disabled t 5 4 40 40 ns max Data Access Time after SCLK Falling Edge t5 0.4 tSCLK 0.4 tSCLK ns min SCLK High Pulsewidth t6 0.4 tSCLK 0.4 tSCLK ns min SCLK Low Pulsewidth t7 10 10 ns min SCLK Edge to Data Valid Hold Time t 6 8 10 10 ns min SCLK Falling Edge to SDATA Three-State Enabled 35 35 ns max SCLK Falling Edge to SDATA Three-State Enabled t 7 POWER-UP 1 1 µs max Power-Up Time from Full Power-Down NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2See Figure 1 and the Serial Interface section. 3Common-mode voltage. 4Mark/space ratio for the SCLK input is 40/60 to 60/40. 5Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7See Power-Up Time section. Specifications subject to change without notice.
t1 CS tCONVERT t2 t5 SCLK 1 2 3 4 5 13 14 15 16 t7 t t 6 8 tQUIET t t 3 4 SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE 4 LEADING ZEROS
Figure 1. Serial Interface Timing Diagram –4– Rev. A