Datasheet AD7450 (Analog Devices) - 4

AD7450 Parameter Conditions/Comments A Version B Version Unit
CONVERSION RATE Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK Cycles 1.07 µs with a 15 MHz SCLK Track-and-Hold Sine Wave Input 200 200 ns max Acquisition Time3, 8 Throughput Rate9 VDD = 5 V 1 1 MSPS max VDD = 3 V 833 833 kSPS max POWER REQUIREMENTS VDD Range: 3 V ± 10%; 5 V ± 5% 3/5 3/5 V min/max I 10, 11 DD Normal Mode (Static) VDD = 3 V/5 V SCLK; ON or OFF 0.5 0.5 mA typ Normal Mode (Operational) VDD = 5 V; fSAMPLE = 1 MSPS 1.8 1.8 mA max VDD = 3 V; fSAMPLE = 833 kSPS 1.25 1.25 mA max Full Power-Down Mode SCLK ON or OFF 1 1 µA max Power Dissipation Normal Mode (Operational) VDD = 5 V; fSAMPLE = 1 MSPS; 9 9 mW max 1.38 mW typ for 100 KSPS10 VDD = 3 V; fSAMPLE = 833 kSPS; 3.75 3.75 mW max 0.53 mW typ for 100 KSPS10 Full Power-Down Mode VDD = 5 V; SCLK ON or OFF 5 5 µW max VDD = 3 V; SCLK ON or OFF 3 3 µW max NOTES 1Temperature range is as follows: A and B Versions: –40°C to +85°C. 2Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9. 3See Terminology section. 4A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto VDD. A 2.2 nF capacitor is used to decouple VDD to GND. 5If the input spans of VIN+ and VIN– are both VREF, and they are 180° out of phase, the differential voltage is 2 ⫻ VREF. 6The AD7450 is functional with a reference input from 100 mV and for V DD = 5 V, the reference can range up to 3.5 V (see References section). 7The AD7450 is functional with a reference input from 100 mV and for V DD = 3 V, the reference can range up to 2.2 V (see References section). 8Sample tested @ 25°C to ensure compliance. 9See Serial Interface section. 10See Power Versus Throughput Rate section. 11Measured with a midscale dc input. Rev. A –3–