Datasheet AD7450 (Analog Devices)

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Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8 AD7450 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast Throughput Rate: 1 MSPS Specified for V V DD of 3 V and 5 V DD Low Power at Max Throughput Rate: 3.75 mW Max at 833 kSPS with 3 V Supplies 9 mW Max at 1 MSPS with 5 V Supplies Fully Differential Analog Input VIN+ Wide Input Bandwidth: T/H 12-BIT SUCCESSIVE APPROXIMATION V 70 dB SINAD at 300 kHz Input Frequency IN– ADC Flexible Power/Serial Clock Speed Management VREF No Pipeline Delays High-Speed Serial Interface—SPITM/QSPITM MICROWIRETM/DSP Compatible SCLK Power-Down Mode: 1 A Max AD7450 CONTROL SDATA 8-Lead SOIC and SOIC Packages LOGIC CS APPLICATIONS Transducer Interface GND Battery-Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications GENERAL DESCRIPTION
The AD7450 is a 12-bit, high-speed, low power, successive The AD7450 uses advanced design techniques to achieve low approximation (SAR) analog-to-digital converter that features a power dissipation at high throughput rates. fully differential analog input. It operates from a single 3 V or 5 V power supply and features throughput rates up to 833 kSPS or
PRODUCT HIGHLIGHTS
1 MSPS, respectively. 1. Operation with either 3 V or 5 V power supplies. This part contains a low noise, wide bandwidth, differential track- 2. High throughput with low power consumption. With a 3 V and-hold amplifier (T/H) that can handle input frequencies in supply, the AD7450 offers 3.75 mW max power consumption excess of 1 MHz with the –3 dB point typically being 20 MHz. for 833 kSPS throughput. The reference voltage for the AD7450 is applied externally to the 3. Fully differential analog input. VREF pin and can be varied from 100 mV to 3.5 V, depending on the power supply and what suits the application. The value of 4. Flexible power/serial clock speed management. The conversion the reference voltage determines the common-mode voltage rate is determined by the serial clock, allowing the power range of the part. With this truly differential input structure and to be reduced as the conversion time is reduced through variable reference input, the user can select a variety of input the serial clock speed increase. This part also features a ranges and bias points. shutdown mode to maximize power efficiency at lower throughput rates. The conversion and data acquisition processes are controlled using CS and the serial clock, allowing the device to interface 5. Variable voltage reference input. with microprocessors or DSPs. The input signals are sampled 6. No pipeline delay. on the falling edge of CS, and the conversion is also initiated at 7. Accurate control of the sampling instant via a CS input and this point. once-off conversion control. The SAR architecture of this part ensures that there are no 8. ENOB > 8 bits typically with 100 mV reference. pipeline delays. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
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