Datasheet AD7485 (Analog Devices)

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1 MSPS, Serial 14-Bit SAR ADC AD7485 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast Throughput Rate: 1 MSPS Wide Input Bandwidth: 40 MHz AVDD AGND CBIAS DVDD V DGND DRIVE Excellent DC Accuracy Performance Flexible Serial Interface Low Power: 2.5 V BUF REFOUT REFERENCE 80 mW (Full Power) and 3 mW (NAP Mode) REFSEL REFIN STANDBY Mode: 2 A Max Single 5 V Supply Operation Internal 2.5 V Reference 14-BIT ALGORITHMIC Full-Scale Overrange Indication VIN T/H SAR AD7485 GENERAL DESCRIPTION MCLK NAP
The AD7485 is a 14-bit, high speed, low power, successive-
TFS
approximation ADC. The part features a serial interface with
STBY CONTROL LOGIC AND I/O SCO
throughput rates up to 1 MSPS. The part contains a low noise,
RESET REGISTERS
wide bandwidth track-and-hold that can handle input frequencies
SDO CONVST
in excess of 40 MHz.
SMODE
The conversion process is a proprietary algorithmic successive- approximation technique. The input signal is sampled and a conversion is initiated on the falling edge of the CONVST signal. The conversion process is controlled by an external master The AD7485 features an on-board 2.5 V reference, but the part can clock. Interfacing is via standard serial signal lines, making the also accommodate an externally provided 2.5 V reference source. part directly compatible with microcontrollers and DSPs. The nominal analog input range is 0 V to 2.5 V. The AD7485 provides excellent ac and dc performance specifi- The AD7485 also provides the user with overrange indication via a cations. Factory trimming ensures high dc accuracy resulting in fifteenth bit. If the analog input range strays outside the 0 V to very low INL, DNL, offset, and gain errors. 2.5 V input range, the fifteenth data bit is set to a logic high. The part uses advanced design techniques to achieve very low The AD7485 is powered from a 4.75 V to 5.25 V supply. The power dissipation at high throughput rates. Power consumption part also provides a VDRIVE pin that allows the user to set the in the normal mode of operation is 80 mW. There are two power- voltage levels for the digital interface lines. The range for this saving modes: a NAP mode keeps reference circuitry alive for VDRIVE pin is from 2.7 V to 5.25 V. The part is housed in a quick power-up and consumes 3 mW, while a STANDBY mode 48-lead LQFP package and is specified over a –40°C to +85°C reduces power consumption to a mere 10 µW. temperature range. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
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2010 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track/Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Typical Performance Characteristics CIRCUIT DESCRIPTION CONVERTER OPERATION ADC TRANSFER FUNCTION POWER SAVING SERIAL INTERFACE Driving the CONVST Pin Board Layout and Grounding OUTLINE DIMENSIONS