Datasheet AD7738 (Analog Devices) - 4

AD7738 Parameter Min Typ Max Unit Test Conditions/Comment
LOGIC INPUTS SCLK, DIN, CS, and RESET Inputs Input Current ±1 µA Input Current CS ±10 µA CS = AVDD –40 µA Internal Pull-Up Resistor Input Capacitance 4 pF V
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T+ 1.4 2 V DVDD = 5 V V
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T– 0.8 1.4 V DVDD = 5 V V
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T+ – VT– 0.3 0.85 V DVDD = 5 V V
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T+ 0.95 2 V DVDD = 3 V V
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T– 0.4 1.1 V DVDD = 3 V V
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T+ – VT– 0.3 0.85 V DVDD = 3 V MCLK IN Only Input Current ±10 µA Input Capacitance 4 pF VINL Input Low Voltage 0.8 V DVDD = 5 V VINH Input High Voltage 3.5 V DVDD = 5 V VINL Input Low Voltage 0.4 V DVDD = 3 V VINH Input High Voltage 2.5 V DVDD = 3 V LOGIC OUTPUTS MCLKOUT
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, DOUT, RDY VOL Output Low Voltage 0.4 V ISINK = 800 µA, DVDD = 5 V VOH Output High Voltage 4.0 V ISOURCE = 200 µA, DVDD = 5 V VOL Output Low Voltage 0.4 V ISINK = 100 µA, DVDD = 3 V VOH Output High Voltage DVDD – 0.6 V ISOURCE = 100 µA, DVDD = 3 V Floating State Leakage Current ±1 µA Floating State Leakage Capacitance 3 pF P1 INPUT Levels Referenced to Analog Supplies Input Current ±10 µA VINL Input Low Voltage 0.8 V AVDD = 5 V VINH Input High Voltage 3.5 V AVDD = 5 V P0, P1 OUTPUT VOL Output Low Voltage 0.4 V ISINK = 8 mA, TMAX = 70°C, AVDD = 5 V 0.4 V ISINK = 5 mA, TMAX = 85°C, AVDD = 5 V 0.4 V ISINK = 2.5 mA, TMAX = 105°C, AVDD = 5 V VOH Output High Voltage 4.0 V ISOURCE = 200 µA, AVDD = 5 V POWER REQUIREMENTS AVDD – AGND Voltage 4.75 5.25 V DVDD – DGND Voltage 4.75 5.25 V 2.70 3.60 V AVDD Current (Normal Mode) 13.6 16 mA AVDD = 5 V AVDD Current (Internal Buffer Off ) 8.5 mA AVDD = 5 V DVDD Current (Normal Mode)
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2.7 3 mA DVDD = 5 V DVDD Current (Normal Mode)
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1.0 1.5 mA DVDD = 3 V AVDD + DVDD Current (Standby Mode)
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80 µA AVDD = DVDD = 5 V Power Dissipation (Normal Mode)
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85 100 mW Power Dissipation (Standby Mode)
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500 µW AVDD = DVDD = 5 V NOTES 1Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release. 2Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise. 3Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error. 4Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise. 5The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max. Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the Mode register. See the register description and circuit description for more details. 6If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. See the circuit description for more details. 7For specified performance. Part is functional with Lower VREF 8Dynamic current charging the sigma-delta modulator input switching capacitor. 9Outside the specified calibration range, calibration is possible but the performance may degrade. 10These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 11With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register). 12External MCLKIN = 0 V or DV , Digital Inputs = 0 V or DV , P0 and P1 = 0 V or AV . DD DD DD Specifications are subject to change without notice. REV. 0 –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS