Datasheet AD7739 (Analog Devices) - 9

AD7739 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 24 DGND MCLKIN 2 23 DVDD MCLKOUT 3 22 DIN 4 CS 21 DOUT 5 RESET 20 RDY AV 6 AD7739 19 DD AGND TOP VIEW 7 AINCOM/P0 (Not to Scale) 18 REFIN(–) SYNC/P1 8 17 REFIN(+) AIN7 9 16 AIN0 AIN6 10 15 AIN1 AIN5 11 14 AIN2 AIN4 12 13 AIN3 03742-0-011
Figure 5. Pin Configuration (24-Lead TSSOP)
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7739. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be left unconnected. 3 MCLKOUT Master Clock Signal for the ADC. When the master clock for the device is a crystal/ resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLKOUT can drive one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AVDD Analog Positive Supply Voltage, 5 V to AGND Nominal. 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The function of this pin is determined by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7 (AIN0 to AIN7) can be referenced to the voltage level of this pin. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the sync bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, tie the pin high or low. 9 to 16 AIN0 to AIN7 Analog Inputs. 17 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a 2.5 V reference voltage. 18 REFIN(−) Negative Terminal of the Differential Reference Input. REFIN(−) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a 0 V reference voltage. Rev. A | Page 8 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Output Noise and Resolution Specification Chopping Enabled Chopping Disabled Register Descriptions Register Access Communications Register 8 Bits, Write-Only Register, Address 0x00 I/O Port Register 8 Bits, Read/Write Register, Address 0x01, Default Value 0x30 + Digital Input Value × 0x40 Revision Register 8 Bits, Read-Only Register, Address 0x02, Default Value 0x09 + Chip Revision × 0x10 Test Register 24 Bits, Read/Write Register, Address 0x03 ADC Status Register 8 Bits, Read-Only Register, Address 0x04, Default Value 0x00 Checksum Register 16 Bits, Read/Write Register, Address 0x05 ADC Zero-Scale Calibration Register 24 Bits, Read/Write Register, Address 0x06, Default Value 0x80 0000 ADC Full-Scale Calibration Register 24 Bits, Read/Write Register, Address 0x07, Default Value 0x80 0000 Channel Data Registers 16-Bit/24-Bit, Read-Only Registers, Address 0x08 to Address 0x0F, Default Width 16 Bits, Default Value 0x8000 Channel Zero-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 0x10 to Address 0x17, Default Value 0x80 0000 Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 0x18 to Address 0x1F, Default Value 0x20 0000 Channel Status Registers 8 Bits, Read-Only Registers, Address 0x20 to Address 0x27, Default Value 0x20 × Channel Number Channel Setup Registers 8 Bits, Read/Write Registers, Address 0x28 to Address 0x2F, Default Value 0x00 Channel Conversion Time Registers 8 Bits, Read/Write Registers, Address 0x30 to Address 0x37, Default Value 0x91 Mode Register 8 Bits, Read/Write Register, Address 0x38 to Address 0x3F, Default Value 0x00 Digital Interface Description Hardware Reset Access the AD7739 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode Circuit Description Analog Inputs Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Extended Voltage Range of the Analog Input Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration ADC Full-Scale Self-Calibration Per Channel System Calibration Outline Dimensions Ordering Guide