Datasheet AD9215 (Analog Devices)

HerstellerAnalog Devices
Beschreibung10-Bit, 65/80/105 MSPS 3 V A/D Converter
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RevisionB
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DokumentenspracheEnglisch

10-Bit, 65/80/105 MSPS,. 3 V A/D Converter. Data Sheet. AD9215. FEATURES. FUNCTIONAL BLOCK DIAGRAM

Datasheet AD9215 Analog Devices, Revision: B

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10-Bit, 65/80/105 MSPS, 3 V A/D Converter Data Sheet AD9215 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 3 V supply operation (2.7 V to 3.3 V) AVDD DRVDD SNR = 58 dBc (to Nyquist) VIN+ SFDR = 77 dBc (to Nyquist) PIPELINE SHA ADC CORE VIN– Low power ADC core: 96 mW at 65 MSPS, 104 mW @ 80 MSPS, 120 mW at 105 MSPS REFT AD9215 Differential input with 300 MHz bandwidth REFB On-chip reference and sample-and-hold amplifier CORRECTION LOGIC DNL = ±0.25 LSB 10 Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS OR Offset binary or twos complement data format D9 (MSB) Clock duty cycle stabilizer D0 VREF CLOCK APPLICATIONS DUTY CYCLE MODE SENSE STABLIZER SELECT Ultrasound equipment REF SELECT 0.5V IF sampling in communications receivers
001 A-
Battery-powered instruments AGND CLK PDWN MODE DGND
02874-
Hand-held scopemeters
Figure 1.
Low cost digital oscilloscopes PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit, Fabricated on an advanced CMOS process, the AD9215 is avail- 65/80/105 MSPS analog-to-digital converters (ADC). This family able in both a 28-lead surface-mount plastic package and a features a high performance sample-and-hold amplifier (SHA) 32-lead chip scale package and is specified over the industrial and voltage reference. The AD9215 uses a multistage differential temperature range of −40°C to +85°C. pipelined architecture with output error correction logic to pro- vide 10-bit accuracy at 105 MSPS data rates and to guarantee no
PRODUCT HIGHLIGHTS
missing codes over the full operating temperature range. 1. The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accom- The wide bandwidth, truly differential sample-and-hold ampli- modate 2.5 V and 3.3 V logic families. fier (SHA) allows for a variety of user-selectable input ranges 2. Operating at 105 MSPS, the AD9215 core ADC consumes and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in a low 120 mW; at 80 MSPS, the power dissipation is 104 mW; and at 65 MSPS, the power dissipation is 96 mW. successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with pow- 3. The patented SHA input maintains excellent performance er and cost savings over previously available ADCs, the AD9215 for input frequencies up to 200 MHz and can be config- is suitable for applications in communications, imaging, and ured for single-ended or differential operation. medical ultrasound. 4. The AD9215 is part of several pin compatible 10-, 12-, and 14-bit low power ADCs. This allows a simplified upgrade A single-ended clock input is used to control all internal conversion from 10 bits to 12 bits for systems up to 80 MSPS. cycles. A duty cycle stabilizer compensates for wide variations in the 5. The clock duty cycle stabilizer maintains converter per- clock duty cycle while maintaining excellent performance. The digital formance over a wide range of clock pulse widths. output data is presented in straight binary or twos complement for- 6. The out of range (OR) output bit indicates when the signal mats. An out-of-range signal indicates an overflow condition, which is beyond the selected input range. can be used with the MSB to determine low or high overflow.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Specifications Absolute Maximum Ratings1 Explanation of Test Levels ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Definitions of Specifications Aperture Delay Aperture Jitter Clock Pulse Width and Duty Cycle Differential Nonlinearity (DNL, No Missing Codes) Effective Number of Bits (ENOB) Gain Error Integral Nonlinearity (INL) Maximum Conversion Rate Minimum Conversion Rate Offset Error Out-of-Range Recovery Time Output Propagation Delay Power Supply Rejection Signal-to-Noise and Distortion (SINAD) Ratio Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Temperature Drift Total Harmonic Distortion (THD) Two-Tone SFDR Typical Performance Characteristics Applying the AD9215 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input and Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board Outline Dimensions Ordering Guide