Datasheet AD7674 (Analog Devices) - 9

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AD7674 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN NI F D ND F U N BUF G U D D B G DD F ND F F B D F C N F F DBUF + C C C – D V E N G + CI CI CI – E E P AV RE DNC AG IN NI NI NI IN RE RE P A R D A NI N N N NI R R 48 47 46 45 44 43 42 41 40 39 38 37 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 AGND 1 36 AGND AGND 1 36 AGND AVDD 2 35 CNVST AVDD 2 35 CNVST MODE0 3 34 PD MODE0 3 34 PD MODE1 4 33 RESET MODE1 4 33 RESET D0/OB/2C 5 AD7674 32 CS WARP 6 TOP VIEW 31 RD D0/OB/2C 5 32 CS AD7674 IMPULSE 7 (Not to Scale) 30 DGND WARP 6 TOP VIEW 31 RD D1/A0 8 29 BUSY (Not to Scale) D2/A1 9 28 D17 IMPULSE 7 30 DGND D3 10 27 D16 D1/A0 8 29 BUSY D4/DIVSCLK[0] 11 26 D15 D5/DIVSCLK[1] 12 25 D14 D2/A1 9 28 D17 D3 10 27 D16 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 D4/DIVSCLK[0] 11 26 D15 T C K N D D D D T K C R I NI N L N D D N U L N D5/DIVSCLK[1] 12 25 D14 O / D Y C V V G G O C Y T S R S / O D O D D S S X / / R VS V C S 1 2 E / E 13 14 15 16 17 18 19 20 21 22 23 24 / N N D 1 I I 0 1 D 6 / / R 1 D D D 7 8 / R C K N D D T K C R / 9 D L D D 3 N D DD U L D /INT N DI ND 1 T Y C S O C D OV DV X S S OG DG D S /SYN RRO E V V S 2 E 1 NOTES /IN /IN D 10/ D11/ D D6/ 7 8 /RDC/ R 1. NIC = NO INTERNAL CONNECTION. D D 9 D 3/ D 2. DNC = DO NOT CONNECT. D1
4
3. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS NOTES
–00
CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
4
1. NIC = NO INTERNAL CONNECTION.
3–0
HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS
–10 –0
2. DNC = DO NOT CONNECT.
308
RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF
00 083
THE SYSTEM.
003 Figure 4. 48-Lead LQFP Pin Configuration Figure 5. 48-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 44 AGND P Analog Power Ground Pin. 2, 47 AVDD P Input Analog Power Pins. Nominally 5 V. 3 MODE0 DI Data Output Interface Mode Selection. 4 MODE1 DI Data Output Interface Mode Selection:
Interface Mode No. MODE1 MODE0 Description
0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 Byte interface 3 1 1 Serial interface 5 D0/OB/2C DI/O In Mode 0, 18-bit interface mode, this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows a choice of straight binary/binary twos complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When this input is high and the IMPULSE pin is low, WARP selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. When low, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Conversion Mode Selection. When this input is high and the WARP pin is low, IMPULSE selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. When the WARP pin and the IMPULSE pin are low, the normal mode is selected. 8 D1/A0 DI/O In Mode 0, 18-bit interface mode, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 9 D2/A1 DI/O In Mode 0, 18-bit interface mode, or Mode 1, 16-bit interface mode, this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 10 D3 DO In all modes except Mode 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. Rev. B | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING Serial Peripheral Interface (SPI) APPLICATIONS INFORMATION LAYOUT EVALUATING AD7674 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES