Datasheet AD7440, AD7450A (Analog Devices) - 3

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Data Sheet AD7440/AD7450A AD7440–SPECIFICA TIONS Table 1. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, V 1 REF = 2.5 V; VCM = VREF; TA = TMIN to TMAX, unless otherwise noted. Temperature range for B Version: –40°C to +85°C. Parameter Test Conditions/Comments B Version Unit
DYNAMIC PERFORMANCE fIN = 100 kHz Signal-to-(Noise + Distortion) (SINAD)2 61 dB min Total Harmonic Distortion (THD)2 –82 dB typ –74 dB max Peak Harmonic or Spurious Noise2 –82 dB typ –76 dB max Intermodulation Distortion (IMD)2 fa = 90 kHz, fb = 110 kHz Second-Order Terms –83 dB typ Third-Order Terms –83 dB typ Aperture Delay2 5 ns typ Aperture Jitter2 50 ps typ Full Power Bandwidth2, 3 @ –3 dB 20 MHz typ @ –0.1 dB 2.5 MHz typ DC ACCURACY Resolution 10 Bits Integral Nonlinearity (INL)2 ±0.5 LSB max Differential Nonlinearity (DNL)2 Guaranteed no missed codes to 10 bits ±0.5 LSB max Zero-Code Error2 ±2.5 LSB max Positive Gain Error2 ±1 LSB max Negative Gain Error2 ±1 LSB max ANALOG INPUT Full-Scale Input Span 2 × V 4 REF VIN+ – VIN– V Absolute Input Voltage VIN+ VCM = VREF VCM ± VREF/2 V VIN– VCM = VREF VCM ± VREF/2 V DC Leakage Current ±1 μA max Input Capacitance When in track-and-hold 30/10 pF typ REFERENCE INPUT VREF Input Voltage VDD = 4.75 V to 5.25 V (±1% tolerance for 2.55 V specified performance) VDD = 2.7 V to 3.6 V (±1% tolerance for specified 2.06 V performance) DC Leakage Current ± 1 μA max VREF Input Capacitance When in track-and-hold 10/30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 μA max Input Capacitance, C 7 IN 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA 2.8 V min VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA 2.4 V min Output Low Voltage, VOL ISINK = 200 μA 0.4 V max Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance7 10 pF max Output Coding Twos complement Rev. D | Page 3 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY AD7440–SPECIFICATIONS AD7450A–SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE GROUNDING AND LAYOUT HINTS EVALUATING THE AD7440/AD7450A PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE