Datasheet AD7652 (Analog Devices) - 9

link to page 17 AD7652 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
F FBUFIN DD FGND F DBUF DRE P P RE TEMP AV IN AGND AGND NC INGND RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 PIN 1 AGND AVDD 2 IDENTIFIER 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS NC 6 AD7652 31 RD NC 7 TOP VIEW 30 (Not to Scale) DGND SER/PAR 8 29 BUSY D0 9 28 D15 10 D1 27 D14 D2/DIVSCLK0 11 26 D13 D3/DIVSCLK1 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT C K IN C /INT D DD T CLK X DOUT VSYN OGND OVDD DV DGND /S RROR /E /S /IN D9 10/SYN D D4 5 /RDC/S D8 /RDE D D6/INVSCL D7 1 D1
02965-0-002 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 6, NC No Connect. 7, 40 4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. 13 D4 or DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE SLAVE SERIAL INTERFACE MICROPROCESSOR INTERFACING APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES LAYOUT EVALUATING THE AD7652’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE