Datasheet AD7938-6 (Analog Devices) - 9

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AD7938-6 Data Sheet Pin No. Mnemonic Description
19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to the internal registers. 21 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7938-6. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 22 VREFIN/VREFOUT Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. It is recommended that this pin be decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog input range does not exceed VDD + 0.3 V. See the Reference section. 23 to 30 VIN0 to VIN7 Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and- hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register appropriately (see Table 9). The analog input channel to be converted can either be selected by writing to the address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be programmed. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 31 VDD Power Supply Input. The VDD range for the AD7938-6 is 2.7 V to 5.25 V. The supply should be decoupled to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor. 32 W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938-6 in 12-bit words on Pin DB0 to Pin DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND. EPAD Exposed Pad. The exposed pad is located on the underside of the package. Connect the EPAD to the ground plane of the PCB using multiple vias. Rev. D | Page 8 of 32 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY ON-CHIP REGISTERS CONTROL REGISTER SEQUENCER OPERATION Writing to the Control Register to Program the Sequencer SHADOW REGISTER CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION Traditional Multichannel Operation (SEQ = 0, SHDW = 0) Using the Sequencer: Programmable Sequence (SEQ = 0, SHDW = 1 ) Consecutive Sequence (SEQ = 1, SHDW = 1) REFERENCE Digital Inputs VDRIVE Input PARALLEL INTERFACE Reading Data from the AD7938-6 Writing Data to the AD7938-6 POWER MODES OF OPERATION Normal Mode (PM1 = PM0 = 0) Autoshutdown (PM1 = 0; PM0 = 1) Autostandby (PM1 = 1; PM0 = 0) Full Shutdown Mode (PM1 =1; PM0 = 1) POWER vs. THROUGHPUT RATE MICROPROCESSOR INTERFACING AD7938-6 to ADSP-21xx Interface AD7938-6 to ADSP-21065L Interface AD7938-6 to TMS32020, TMS320C25, and TMS320C5x Interface AD7938-6 to 80C186 Interface APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE EVALUATING THE AD7938-6 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE