Datasheet AD9289 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter |
| Seiten / Seite | 33 / 6 — AD9289. SWITCHING SPECIFICATIONS. Table 4. Parameter Temp. Test. Level. … |
| Dateiformat / Größe | PDF / 934 Kb |
| Dokumentensprache | Englisch |
AD9289. SWITCHING SPECIFICATIONS. Table 4. Parameter Temp. Test. Level. Min. Typ. Max. Unit. TIMING DIAGRAMS. N-1. AIN. tEH. tEL. CLK–. CLK+. tCPD. DCO–
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AD9289 SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.
Table 4. Parameter Temp Test Level Min Typ Max Unit
CLOCK Maximum Clock Rate Full VI 65 MSPS Minimum Clock Rate Full IV 12 MSPS Clock Pulse Width High (tEH) Full VI 6.9 7.7 ns Clock Pulse Width Low (tEL) Full VI 6.9 7.7 ns OUTPUT PARAMETERS Valid Time (tV)1 Full IV 0.5 <1.5 CLK cycles Propagation Delay (tPD) Full VI 6.9 9.0 11.6 ns Rise Time (tR) (20% to 80%) Full V 250 ps Fall Time (tF) (20% to 80%) Full V 250 ps FCO Propagation Delay (tFCO) Full V 9.0 ns DCO Propagation Delay (tCPD) Full V 9.0 ns DCO-to-Data Delay (tDATA) Full VI ±100 ±550 ps DCO-to-FCO Delay (tFRAME) Full VI ±100 ±500 ps Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Full IV ±100 ±250 ps PLL Lock Time (tLOCK) 25°C V 1.8 µs Wake-Up Time 25°C V 7 ms Pipeline Latency Full IV 6 CLK cycles APERTURE Aperture Delay (tA) 25°C V 4.5 ns Aperture Uncertainty (Jitter) 25°C V <1 ps rms OUT-OF-RANGE RECOVERY TIME 25°C V 1 CLK cycles 1 Actual valid time is dependent on the moment when LOCK goes low.
TIMING DIAGRAMS N-1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– STATIC STATIC DCO+ t t FCO FRAME FCO– STATIC STATIC FCO+ t t PD DATA D1– MSB D6 D5 D4 D3 D2 D1 LSB MSB STATIC INVALID (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-6) STATIC D1+ LOCK tV
03682-003 Figure 2. Timing Diagram Rev. 0 | Page 5 of 32 Document Outline FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS Power Dissipation and Standby Mode Digital Outputs Timing Pin CML Pin DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9289 SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.
Table 4. Parameter Temp Test Level Min Typ Max Unit
CLOCK Maximum Clock Rate Full VI 65 MSPS Minimum Clock Rate Full IV 12 MSPS Clock Pulse Width High (tEH) Full VI 6.9 7.7 ns Clock Pulse Width Low (tEL) Full VI 6.9 7.7 ns OUTPUT PARAMETERS Valid Time (tV)1 Full IV 0.5 <1.5 CLK cycles Propagation Delay (tPD) Full VI 6.9 9.0 11.6 ns Rise Time (tR) (20% to 80%) Full V 250 ps Fall Time (tF) (20% to 80%) Full V 250 ps FCO Propagation Delay (tFCO) Full V 9.0 ns DCO Propagation Delay (tCPD) Full V 9.0 ns DCO-to-Data Delay (tDATA) Full VI ±100 ±550 ps DCO-to-FCO Delay (tFRAME) Full VI ±100 ±500 ps Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Full IV ±100 ±250 ps PLL Lock Time (tLOCK) 25°C V 1.8 µs Wake-Up Time 25°C V 7 ms Pipeline Latency Full IV 6 CLK cycles APERTURE Aperture Delay (tA) 25°C V 4.5 ns Aperture Uncertainty (Jitter) 25°C V <1 ps rms OUT-OF-RANGE RECOVERY TIME 25°C V 1 CLK cycles 1 Actual valid time is dependent on the moment when LOCK goes low.
TIMING DIAGRAMS N-1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– STATIC STATIC DCO+ t t FCO FRAME FCO– STATIC STATIC FCO+ t t PD DATA D1– MSB D6 D5 D4 D3 D2 D1 LSB MSB STATIC INVALID (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-6) STATIC D1+ LOCK tV
03682-003 Figure 2. Timing Diagram Rev. 0 | Page 5 of 32 Document Outline FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS Power Dissipation and Standby Mode Digital Outputs Timing Pin CML Pin DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE