Datasheet AD9229 (Analog Devices)

Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter AD9229 FEATURES FUNCTIONAL BLOCK DIAGRAM Four ADCs in 1 package PDWN DTP DRVDD DRGND Serial LVDS digital output data rates to 780 Mbps (ANSI-644) AD9229 Data and frame clock outputs VIN+A 12 D+A SERIAL SHA PIPELINE VIN–A ADC LVDS D–A SNR = 69.5 dB (to Nyquist) Excellent linearity VIN+B 12 D+B SERIAL SHA PIPELINE DNL = ±0.3 LSB (typical) VIN–B ADC LVDS D–B INL = ±0.4 LSB (typical) VIN+C 12 D+C SERIAL 400 MHz full power analog bandwidth SHA PIPELINE VIN–C ADC LVDS D–C Power dissipation VIN+D 12 D+D 1,350 mW at 65 MSPS SERIAL SHA PIPELINE VIN–D ADC LVDS D–D 985 mW at 50 MSPS 1 V p-p to 2 V p-p input voltage range VREF 3.0 V supply operation SENSE FCO+ 0.5V Power-down mode FCO– REFT DATA RATE REF Digital test pattern enable for timing alignments MULTIPLIER SELECT DCO+ REFB DCO– APPLICATIONS Digital beam-forming systems for ultrasound AGND LVDSBIAS CLK
04418-001
Wireless and wired broadband communications
Figure 1.
Communication test equipment GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital 1. Four ADCs are contained in a small, space-saving package. converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. 2. A data clock out (DCO) is provided, which operates up to The product operates at up to a 65 MSPS conversion rate and is 390 MHz and supports double-data rate operation (DDR). optimized for outstanding dynamic performance in applications 3. The outputs of each ADC are serialized LVDS with data where a small package size is critical. rates up to 780 Mbps (12 bits × 65 MSPS). The ADC requires a single 3 V power supply and TTL-/CMOS- 4. The AD9229 operates from a single 3.0 V power supply. compatible sample rate clock for full performance operation. No external reference or driver components are required for 5. Packaged in a Pb-free, 48-lead LFCSP package. many applications. 6. The internal clock duty cycle stabilizer maintains The ADC automatically multiplies the sample rate clock for the performance over a wide range of input clock duty cycles. appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled. Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Power Dissipation and Power-Down Mode Digital Outputs Timing DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATE ANALOG INPUT DRIVE CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE