Datasheet AD7760 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer |
| Seiten / Seite | 37 / 10 — 64 63 62. 61 60 59 58. 57 56 55 54 53 52 51 50 49. DGND 1. DB12. MCLKGND … |
| Revision | A |
| Dateiformat / Größe | PDF / 866 Kb |
| Dokumentensprache | Englisch |
64 63 62. 61 60 59 58. 57 56 55 54 53 52 51 50 49. DGND 1. DB12. MCLKGND 2. PIN 1. 47 DB13. MCLK 3. DB14. 45 DB15. DD2. AGND2 5. 44 VDRIVE. 43 DGND
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AD7760 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D E D D N IV 0 1 R N 0 1 2 3 4 5 6 7 N 8 9 1 1 G D G B B B B B B B B G B B B B D V D D D D D D D D D D D D D D 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND 1 48 DB12 MCLKGND 2 PIN 1 47 DB13 MCLK 3 46 DB14 AV 4 45 DB15 DD2 AGND2 5 44 VDRIVE AV 6 43 DGND DD1 AGND1 7 42 DGND AD7760 DECAPA 8 41 DV TOP VIEW DD REFGND (Not to Scale) 9 40 CS V 10 39 RD/WR REF+ AGND4 11 38 DRDY AV 12 37 RESET DD4 AGND2 13 36 SYNC AV 14 35 DGND DD2 AV 15 34 AGND1 DD2 AGND2 16 33 AVDD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S 2 + – – + 3 3 + – 2 2 3 B 3 3 IA D A A A A D D IN IN D D D P D D
5
B N IN IN T T N D V V D N N A N N
0
R G V V U U G V V G G
-0
C G G
5
A O O A A
7
V V A A A E A A
9
D
4 0 Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
6, 33 AVDD1 2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively) with 100 nF and 10 µF capacitors on each pin. See the Decoupling and Layout Recommendations section for details. 4, 14, 15, 27 AVDD2 5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the Decoupling and Layout Recommendations section for details. 24 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a 100 nF capacitor. See the Decoupling and Layout Recommendations section for details. 12 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor in series with a 10 Ω resistor. 7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AVDD1. 5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2. 23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3. 11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4. 9 REFGND Reference Ground. Ground connection for the reference voltage. 41 DVDD 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF capacitor. 44, 63 VDRIVE Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating voltage of the logic interface. Both of these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a 100 nF capacitor. 1, 35, 42, 43, DGND Ground Reference for Digital Circuitry. 53, 62, 64 19 VINA+ Positive Input to Differential Amplifier. 20 VINA− Negative Input to Differential Amplifier. 21 VOUTA− Negative Output from Differential Amplifier. 22 VOUTA+ Positive Output from Differential Amplifier. 25 VIN+ Positive Input to the Modulator. 26 VIN− Negative Input to the Modulator. 10 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See the Reference Voltage Filtering section for more details. 8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND. Rev. A | Page 9 of 36
D E D D N IV 0 1 R N 0 1 2 3 4 5 6 7 N 8 9 1 1 G D G B B B B B B B B G B B B B D V D D D D D D D D D D D D D D 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND 1 48 DB12 MCLKGND 2 PIN 1 47 DB13 MCLK 3 46 DB14 AV 4 45 DB15 DD2 AGND2 5 44 VDRIVE AV 6 43 DGND DD1 AGND1 7 42 DGND AD7760 DECAPA 8 41 DV TOP VIEW DD REFGND (Not to Scale) 9 40 CS V 10 39 RD/WR REF+ AGND4 11 38 DRDY AV 12 37 RESET DD4 AGND2 13 36 SYNC AV 14 35 DGND DD2 AV 15 34 AGND1 DD2 AGND2 16 33 AVDD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S 2 + – – + 3 3 + – 2 2 3 B 3 3 IA D A A A A D D IN IN D D D P D D
5
B N IN IN T T N D V V D N N A N N
0
R G V V U U G V V G G
-0
C G G
5
A O O A A
7
V V A A A E A A
9
D
4 0 Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
6, 33 AVDD1 2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively) with 100 nF and 10 µF capacitors on each pin. See the Decoupling and Layout Recommendations section for details. 4, 14, 15, 27 AVDD2 5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the Decoupling and Layout Recommendations section for details. 24 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a 100 nF capacitor. See the Decoupling and Layout Recommendations section for details. 12 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor in series with a 10 Ω resistor. 7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AVDD1. 5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2. 23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3. 11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4. 9 REFGND Reference Ground. Ground connection for the reference voltage. 41 DVDD 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF capacitor. 44, 63 VDRIVE Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating voltage of the logic interface. Both of these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a 100 nF capacitor. 1, 35, 42, 43, DGND Ground Reference for Digital Circuitry. 53, 62, 64 19 VINA+ Positive Input to Differential Amplifier. 20 VINA− Negative Input to Differential Amplifier. 21 VOUTA− Negative Output from Differential Amplifier. 22 VOUTA+ Positive Output from Differential Amplifier. 25 VIN+ Positive Input to the Modulator. 26 VIN− Negative Input to the Modulator. 10 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See the Reference Voltage Filtering section for more details. 8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND. Rev. A | Page 9 of 36