Datasheet AD9237 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 20/40/65 MSPS 3 V Low Power A/D Converter |
| Seiten / Seite | 25 / 9 — AD9237. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. MODE2 1. … |
| Revision | C |
| Dateiformat / Größe | PDF / 620 Kb |
| Dokumentensprache | Englisch |
AD9237. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. MODE2 1. 24 VREF. CLK 2. 23 SENSE. OE 3. 22 MODE. PDWN 4. 21 OTR. TOP VIEW
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AD9237 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D D D T B D N – + N D F F V G NI NI G V E E A A V V A A R R 32 31 30 29 28 27 26 25 MODE2 1 24 VREF CLK 2 23 SENSE OE 3 22 MODE AD9237 PDWN 4 21 OTR TOP VIEW GC 5 20 D11 (MSB) (Not to Scale) DNC 6 19 D10 D0 (LSB) 7 18 D9 D1 8 17 D8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 D D D D D D D D N D G V D R D NOTES
3
1. DNC = DO NOT CONNECT.
00 5-
2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE.
545 0 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin Number Mnemonic Description
1 MODE2 SHA Gain Select and Power Scaling Control (see Table 8). 2 CLK Clock Input Pin. 3 OE Output Enable Pin (Active Low). 4 PDWN Power-Down Function Selection (see Table 9). 5 GC Gray Code Control (Active High). 6 DNC Do Not Connect. 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits. 15 DGND Digital Output Ground. 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 21 OTR Out-of-Range Indicator. 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10). 23 SENSE Reference Mode Selection (see Table 7). 24 VREF Voltage Reference Input/Output (see Table 7). 25 REFB Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor. 26 REFT Differential Reference (+). 27, 32 AVDD Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 28, 31 AGND Analog Ground. 29 VIN+ Analog Input Pin (+). 30 VIN− Analog Input Pin (−). EP It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. Rev. C | Page 8 of 24 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications DC Specifications Digital Specifications AC Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Equivalent Circuits Typical Performance Characteristics Applying the AD9237 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Power Dissipation, Power Scaling, and Standby Mode Digital Outputs Operational Mode Selection Out of Range (OTR) Digital Output Enable Function (OE) Timing Outline Dimensions Ordering Guide
AD9237 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D D D T B D N – + N D F F V G NI NI G V E E A A V V A A R R 32 31 30 29 28 27 26 25 MODE2 1 24 VREF CLK 2 23 SENSE OE 3 22 MODE AD9237 PDWN 4 21 OTR TOP VIEW GC 5 20 D11 (MSB) (Not to Scale) DNC 6 19 D10 D0 (LSB) 7 18 D9 D1 8 17 D8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 D D D D D D D D N D G V D R D NOTES
3
1. DNC = DO NOT CONNECT.
00 5-
2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE.
545 0 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin Number Mnemonic Description
1 MODE2 SHA Gain Select and Power Scaling Control (see Table 8). 2 CLK Clock Input Pin. 3 OE Output Enable Pin (Active Low). 4 PDWN Power-Down Function Selection (see Table 9). 5 GC Gray Code Control (Active High). 6 DNC Do Not Connect. 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits. 15 DGND Digital Output Ground. 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 21 OTR Out-of-Range Indicator. 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10). 23 SENSE Reference Mode Selection (see Table 7). 24 VREF Voltage Reference Input/Output (see Table 7). 25 REFB Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor. 26 REFT Differential Reference (+). 27, 32 AVDD Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 28, 31 AGND Analog Ground. 29 VIN+ Analog Input Pin (+). 30 VIN− Analog Input Pin (−). EP It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. Rev. C | Page 8 of 24 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications DC Specifications Digital Specifications AC Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Equivalent Circuits Typical Performance Characteristics Applying the AD9237 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Power Dissipation, Power Scaling, and Standby Mode Digital Outputs Operational Mode Selection Out of Range (OTR) Digital Output Enable Function (OE) Timing Outline Dimensions Ordering Guide