Datasheet AD9446 (Analog Devices)

16-Bit, 80/100 MSPS ADC AD9446 FEATURES FUNCTIONAL BLOCK DIAGRAM 100 MSPS guaranteed sampling rate (AD9446-100) AGND AVDD1 AVDD2 DRGND DRVDD 83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS) AD9446 DFS 82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS) DCS MODE 89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS) BUFFER OUTPUT MODE VIN+ 16 PIPELINE 2 95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS) T/H CMOS OR VIN– ADC OR 60 fsec rms jitter LVDS 32 OUTPUT D15 TO D0 Excellent linearity STAGING 2 DNL = ±0.4 LSB typical CLOCK CLK+ DCO AND TIMING REF INL = ±3.0 LSB typical CLK– MANAGEMENT 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs VREF SENSE REFT REFB
05490-001
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Figure 1.
Data format select (offset binary or twos complement) Output clock available 3.3 V and 5 V supply operation
Optional features allow users to implement various selectable
APPLICATIONS
operating conditions, including input range, data format select,
MRI receivers
and output data mode.
Multicarrier, multimode cellular receivers
The AD9446 is available in a Pb-free, 100-lead, surface-mount,
Antenna array positioning
plastic package (100-lead TQFP/EP) specified over the
Power amplifier linearization
industrial temperature range −40°C to +85°C.
Broadband wireless Radar PRODUCT HIGHLIGHTS Infrared imaging Communications instrumentation
1. True 16-bit linearity.
GENERAL DESCRIPTION
2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, The AD9446 is a 16-bit, monolithic, sampling analog-to-digital magnetic resonance imaging, and radar receivers. converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The 3. Ease of use: on-chip reference and high input impedance product operates up to a 100 MSPS, providing superior SNR for track-and-hold with adjustable analog input range and an instrumentation, medical imaging, and radar receivers output clock simplifies data capture. employing baseband (<100 MHz) IF frequencies. 4. Packaged in a Pb-free, 100-lead TQFP/EP package. The ADC requires 3.3 V and 5.0 V power supplies and a low 5. Clock duty cycle stabilizer (DCS) maintains overall ADC voltage differential input clock for full performance operation. performance over a wide range of clock pulse widths. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS 6. OR (out-of-range) outputs indicate when the signal is compatible (ANSI-644 compatible) and include the means to beyond the selected input range. reduce the overall current needed for short trace distances.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TERMINOLOGY PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE