Datasheet AD7641 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 18-Bit, 2 MSPS SAR ADC |
| Seiten / Seite | 29 / 9 — AD7641. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. DBUF. DRE. 48 … |
| Dateiformat / Größe | PDF / 549 Kb |
| Dokumentensprache | Englisch |
AD7641. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. DBUF. DRE. 48 47 46 45 44 43 42 41 40 39 38 37. AGND 1. 36 AGND. PIN 1. AVDD 2
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AD7641 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND BUF P D G F M D ND ND F F DBUF DRE + – P P RE TE AV IN AG AG NC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS WARP 6 AD7641 31 RD TOP VIEW NORMAL 7 30 (Not to Scale) DGND D1/A0 8 29 BUSY D2/A1 9 28 D17 D3 10 27 D16 D4/DIVSCLK[0] 11 26 D15 D5/DIVSCLK[1] 12 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT T C K IN D D T R /IN D N D DD ND U LK NC T CL S O Y X S OV DV D VSYN V OG DG S 1/SC /S RRO 6/E IN D1
04
D 7/IN RDC/ D12 /RDE
0
D D8/ D10/
1-
D9/
76
D13
04 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type
1
Description
1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI Data Output Interface Mode Selection.
Interface MODE# MODE1 MODE0 Description
0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface 5 D0/OB/2C DI/O When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary/twos complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. 7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 8 D1/A0 DI/O When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 D0 When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. or DIVSCLK[0:1] When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7641 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND BUF P D G F M D ND ND F F DBUF DRE + – P P RE TE AV IN AG AG NC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS WARP 6 AD7641 31 RD TOP VIEW NORMAL 7 30 (Not to Scale) DGND D1/A0 8 29 BUSY D2/A1 9 28 D17 D3 10 27 D16 D4/DIVSCLK[0] 11 26 D15 D5/DIVSCLK[1] 12 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT T C K IN D D T R /IN D N D DD ND U LK NC T CL S O Y X S OV DV D VSYN V OG DG S 1/SC /S RRO 6/E IN D1
04
D 7/IN RDC/ D12 /RDE
0
D D8/ D10/
1-
D9/
76
D13
04 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type
1
Description
1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI Data Output Interface Mode Selection.
Interface MODE# MODE1 MODE0 Description
0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface 5 D0/OB/2C DI/O When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary/twos complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. 7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 8 D1/A0 DI/O When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 D0 When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. or DIVSCLK[0:1] When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7641 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE