link to page 18 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 23 link to page 23 Data SheetAD7329B VersionParameter1MinTypMaxUnitTest Conditions/Comments ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range ±10 V VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V Register) ±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V ±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V 0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V Pseudo Differential VIN− VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 43 and Input Range Figure 44 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±100 nA VIN = VDD or VSS 3 nA Per channel, VIN = VDD or VSS Input Capacitance3 16 pF When in track, all ranges, single ended ADCIN± Capacitance3 7 pF When in track, ±10 V range, single ended 10 pF When in track, ±5 V range, single ended 14.5 pF When in track, ±2.5 V range, single ended 10.5 pF When in track, 0 V to +10 V range, single ended 4.0 pF When in hold, all ranges, single ended MUXOUT− Capacitance3 7.5 pF All ranges, single ended MUXOUT+ Capacitance3 13 pF All ranges, single ended REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 µA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error ±5 mV at 25°C Reference Output Voltage ±10 mV TMIN to TMAX Reference Temperature 25 ppm/°C Coefficient 3 ppm/°C Reference Output Impedance 7 Ω LOGIC INPUTS Input High Voltage, VINH 2.4 V Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V 0.4 V VCC = 2.7 to 3.6 V Input Current, IIN ±1 µA VIN = 0 V or VDRIVE Input Capacitance, C 3 IN 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − V ISOURCE = 200 µA 0.2 V Output Low Voltage, VOL 0.4 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output 5 pF Capacitance3 Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register Rev. C | Page 5 of 38 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION OUTPUT CODING TRANSFER FUNCTIONS ANALOG INPUT STRUCTURE TRACK-AND-HOLD SECTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Single-Ended Inputs True Differential Mode Pseudo Differential Inputs DRIVER AMPLIFIER CHOICE REGISTERS ADDRESSING REGISTERS CONTROL REGISTER SEQUENCE REGISTER RANGE REGISTERS SEQUENCER OPERATION REFERENCE VDRIVE TEMPERATURE INDICATOR MODES OF OPERATION NORMAL MODE(PM1 = PM0 = 0) FULL SHUTDOWN MODE(PM1 = PM0 = 1) AUTOSHUTDOWN MODE(PM1 = 1, PM0 = 0) AUTOSTANDBY MODE(PM1 = 0, PM0 =1) POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7329 TO ADSP-21xx AD7329 TO ADSP-BF53x APPLICATIONS INFORMATION LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE