Datasheet AD7643 (Analog Devices) - 6

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AD7643 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 30 and Figure 31) Convert Pulse Width t1 15 701 ns Time Between Conversions t2 800 ns CNVST Low to BUSY High Delay t3 23 ns BUSY High All Modes (Except Master Serial Read After Convert) t4 550 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t7 550 ns Acquisition Time t8 250 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay2 t38 10 ns BUSY High Time from RESET Low2 t39 500 ns PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 ) CNVST Low to Data Valid Delay t10 550 ns Data Valid to BUSY Low Delay t11 2 ns Bus Access Request to Data Valid t12 20 ns Bus Relinquish Time t13 2 15 ns MASTER SERIAL INTERFACE MODES3 (Refer to Figure 36 and Figure 37) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SCLK Valid Delay3 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay t17 135 ns SYNC Asserted to SCLK First Edge Delay t18 2 ns Internal SCLK Period4 t19 8 20 ns Internal SCLK High4 t20 2 ns Internal SCLK Low4 t21 2 ns SDOUT Valid Setup Time4 t22 1 ns SDOUT Valid Hold Time4 t23 0 ns SCLK Last Edge to SYNC Delay4 t24 0 ns CS High to SYNC Hi-Z t25 10 ns CS High to Internal SCLK Hi-Z t26 10 ns CS High to SDOUT Hi-Z t27 10 ns BUSY High in Master Serial Read After Convert4 t28 See Table 4 ns CNVST Low to SYNC Asserted Delay t29 508 ns SYNC Deasserted to BUSY Low Delay t30 13 ns SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40) External SCLK Set-Up Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Set-Up Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 12.5 ns External SCLK High t36 5 ns External SCLK Low t37 5 ns 1 See the Conversion Control section. 2 See the Digital Interface section and the RESET section. 3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS MULTIPLEXED INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) External 2.5 V Reference (PDBUF = High, PDREF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7643 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE