Datasheet AD9233 (Analog Devices) - 10

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AD9233 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DD ND – + B DD ND DD K K ND DRV DRG NC NC DCO OE AV AG AV CL CL AG 48 47 46 45 44 43 42 41 40 39 38 37 (LSB) D0 1 36 PDWN PIN 1 D1 2 INDICATOR 35 RBIAS D2 3 34 CML D3 4 33 AVDD D4 5 32 AGND D5 6 AD9233 31 VIN– DRGND 7 TOP VIEW 30 VIN+ DRVDD 8 (Not to Scale) 29 AGND D6 9 28 REFT D7 10 27 REFB D8 11 26 VREF PIN 0 (EXPOSED PADDLE): AGND D9 12 25 SENSE 13 14 15 16 17 18 19 20 21 22 23 24 11 D S S B D10 OR ND D C F ND DD ND DD ) D V /D /D CS K AG AV AG AV SB DRG DR IO D L
03
(M S SC
0 2- 49 05
NC = NO CONNECT
Figure 3. Pin Configuration
Table 7. Pin Function Description Pin No. Mnemonic Description
0, 21, 23, 29, AGND Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.) 32, 37, 41 1 to 6, 9 to 14 D0 (LSB) to D11 (MSB) Data Output Bits. 7, 16, 47 DRGND Digital Output Ground. 8, 17, 48 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 15 OR Out-of-Range Indicator. 18 SDIO/DCS Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). See Table 10. 19 SCLK/DFS SPI Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). See Table 10. 20 CSB SPI Chip Select (Active Low). 22, 24, 33, 40, 42 AVDD Analog Power Supply. 25 SENSE Reference Mode Selection. See Table 9. 26 VREF Voltage Reference Input/Output. 27 REFB Differential Reference (−). 28 REFT Differential Reference (+). 30 VIN+ Analog Input Pin (+). 31 VIN– Analog Input Pin (−). 34 CML Common-Mode Level Bias Output. 35 RBIAS External Bias Resister Connection. A 10 kΩ resister must be connected between this pin and analog ground (AGND). 36 PDWN Power-Down Function Select. 38 CLK+ Clock Input (+). 39 CLK– Clock Input (−). 43 OEB Output Enable (Active Low). 44 DCO Data Clock Output. 45, 46 NC No Connection. Rev. A | Page 9 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Clock Duty Cycle JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE Power-Down Mode Standby Mode DIGITAL OUTPUTS Out-of-Range (OR) Condition Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels SPI-Accessible Features LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN VREF RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE