Datasheet AD9259 (Analog Devices)

Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC Data Sheet AD9259 FEATURES FUNCTIONAL BLOCK DIAGRAM 4 ADCs integrated into 1 package AVDD PDWN DRVDD DRGND 98 mW ADC power per channel at 50 MSPS AD9259 SNR = 73 dB (to Nyquist) 14 VIN + A PIPELINE SERIAL D + A ENOB = 12 bits T/H VIN – A ADC LVDS D – A SFDR = 84 dBc (to Nyquist) 14 VIN + B Excellent linearity PIPELINE SERIAL D + B T/H VIN – B ADC LVDS D – B DNL = ±0.5 LSB (typical) 14 INL = ±1.5 LSB (typical) VIN + C PIPELINE SERIAL D + C T/H VIN – C ADC LVDS D – C Serial LVDS (ANSI-644, default) 14 Low power, reduced signal option (similar to IEEE 1596.3) VIN + D SERIAL PIPELINE D + D T/H LVDS D – D Data and frame clock outputs VIN – D ADC 315 MHz full-power analog bandwidth VREF SENSE FCO+ 2 V p-p input voltage range +– 0.5V FCO– DATA RATE 1.8 V supply operation REFT REF MULTIPLIER REFB SELECT SERIAL PORT DCO+ Serial port control INTERFACE DCO– Full-chip and individual-channel power-down modes
1 00 65-
Flexible bit orientation RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
059
Built-in and custom digital test pattern generation
Figure 1.
Programmable clock and data alignment
The ADC automatically multiplies the sample rate clock for the
Programmable output resolution
appropriate LVDS serial data rate. A data clock output (DCO) for
Standby mode
capturing data on the output and a frame clock output (FCO)
APPLICATIONS
for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW
Medical imaging and nondestructive ultrasound
when all channels are disabled.
Portable ultrasound and digital beam-forming systems Quadrature radio receivers
The ADC contains several features designed to maximize
Diversity radio receivers
flexibility and minimize system cost, such as programmable
Tape drives
clock and data alignment and programmable digital test pattern
Optical networking
generation. The available digital test patterns include built-in
Test equipment
deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).
GENERAL DESCRIPTION
The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con- specified over the industrial temperature range of −40°C to +85°C. verter (ADC) with an on-chip sample-and-hold circuit designed
PRODUCT HIGHLIGHTS
for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for 1. Small Footprint. Four ADCs are contained in a small, space- outstanding dynamic performance and low power in applications saving package. where a small package size is critical. 2. Low power of 98 mW/channel at 50 MSPS. 3. Ease of Use. A data clock output (DCO) operates at The ADC requires a single 1.8 V power supply and LVPECL-/ frequencies of up to 350 MHz and supports double data CMOS-/LVDS-compatible sample rate clock for full performance rate (DDR) operation. operation. No external reference or driver components are 4. User Flexibility. The SPI control offers a wide range of flexible required for many applications. features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit).
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide