Datasheet AD9287 (Analog Devices)

Quad, 8-Bit, 100 MSPS, Serial LVDS 1.8 V ADC Data Sheet AD9287 FEATURES FUNCTIONAL BLOCK DIAGRAM 4 ADCs integrated into 1 package AVDD PDWN DRVDD DRGND 133 mW ADC power per channel at 100 MSPS AD9287 SNR = 49 dB (to Nyquist) 8 VIN + A PIPELINE SERIAL D + A ENOB = 7.85 bits T/H VIN – A ADC LVDS D – A SFDR = 65 dBc (to Nyquist) 8 Excellent linearity VIN + B PIPELINE SERIAL D + B T/H VIN – B ADC LVDS D – B DNL = ±0.2 LSB (typical) 8 INL = ±0.2 LSB (typical) VIN + C PIPELINE SERIAL D + C T/H ADC LVDS D – C Serial LVDS (ANSI-644, default) VIN – C Low power, reduced signal option (similar to IEEE 1596.3) 8 VIN + D SERIAL PIPELINE D + D T/H Data and frame clock outputs VIN – D LVDS D – D ADC 295 MHz full-power analog bandwidth VREF 2 V p-p input voltage range SENSE FCO+ + – 0.5V FCO– 1.8 V supply operation DATA RATE REFT REF MULTIPLIER Serial port control REFB SELECT SERIAL PORT DCO+ INTERFACE DCO– Full-chip and individual-channel power-down modes
001
Flexible bit orientation RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
05966-
Built-in and custom digital test pattern generation
Figure 1.
Programmable clock and data alignment Programmable output resolution
capturing data on the output and a frame clock output (FCO)
Standby mode
for signaling a new output byte are provided. Individual-channel
APPLICATIONS
power-down is supported and typically consumes less than 2 mW when all channels are disabled.
Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems
The ADC contains several features designed to maximize
Quadrature radio receivers
flexibility and minimize system cost, such as programmable
Diversity radio receivers
clock and data alignment and programmable digital test pattern
Tape drives
generation. The available digital test patterns include built-in
Optical networking
deterministic and pseudorandom patterns, along with custom user-
Test equipment
defined test patterns entered via the serial port interface (SPI).
GENERAL DESCRIPTION
The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con- is specified over the industrial temperature range of −40°C to verter (ADC) with an on-chip sample-and-hold circuit designed +85°C. for low cost, low power, small size, and ease of use. The product
PRODUCT HIGHLIGHTS
operates at a conversion rate of up to 100 MSPS and is optimized 1. for outstanding dynamic performance and low power in Small Footprint. Four ADCs are contained in a small, space- saving package. applications where a small package size is critical. 2. Low power of 133 mW/channel at 100 MSPS. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. Ease of Use. A data clock output (DCO) is provided that CMOS-/LVDS-compatible sample rate clock for full performance operates at frequencies of up to 400 MHz and supports operation. No external reference or driver components are double data rate (DDR) operation. required for many applications. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. The ADC automatically multiplies the sample rate clock for the 5. Pin-Compatible Family. This includes the AD9219 (10-bit), appropriate LVDS serial data rate. A data clock output (DCO) for AD9228 (12-bit), and AD9259 (14-bit).
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE