Datasheet AD7610 (Analog Devices) - 7

AD7610 Data Sheet Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t20 15 30 60 120 ns Internal SDCLK Low Minimum t21 10 25 55 115 ns SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 2.25 3.00 4.40 7.30 μs
1.6mA IOL TO OUTPUT 1.4V PIN CL 60pF 2V 500µA IOH 0.8V t NOTES DELAY tDELAY 1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
3 02
2V 2V
00
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
-0 5-
0.8V 0.8V
39
C
95
L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
63 06 0 Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. A | Page 6 of 32 Document Outline Features Functional Block Diagram Applications General Description Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Input Range Selection Input Structure Voltage Reference Input/Output Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor Power Supplies Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down Conversion Control Interfaces Digital Interface RESET Parallel Interface Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Serial Interface Data Interface Master Serial Interface Internal Clock (SER/ = High, EXT/ = Low) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) Read During Convert (RDC = High) Slave Serial Interface External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion Hardware Configuration Software Configuration Microprocessor Interfacing SPI Interface Application Information Layout Guidelines Evaluating Performance Outline Dimensions Ordering Guide