Datasheet AD7610 (Analog Devices) - 5

link to page 20 link to page 7 link to page 5 link to page 5 link to page 5 link to page 5
AD7610 Data Sheet Parameter Conditions/Comments Min Typ Max Unit
EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 250 kSPS throughput 30 µA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels VIL −0.3 +0.6 V VIH 2.1 OVDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS Data Format Parallel or serial 16-bit Pipeline Delay5 VOL ISINK = 500 µA 0.4 V VOH ISOURCE = –500 µA OVDD − 0.6 V POWER SUPPLIES Specified Performance AVDD 4.756 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V Operating Current7, 8 @ 250 kSPS throughput AVDD With Internal Reference 8 mA With Internal Reference Disabled 6.3 mA DVDD 3.3 mA OVDD 0.3 mA VCC VCC = 15 V, with internal reference buffer 1.4 mA VCC = 15 V 0.8 mA VEE VEE = −15 V 0.7 mA Power Dissipation @ 250 kSPS throughput With Internal Reference PDREF = PDBUF = low 90 110 mW With Internal Reference Disabled PDREF = PDBUF = high 70 90 mW In Power-Down Mode9 PD = high 10 µW TEMPERATURE RANGE10 Specified Performance TMIN to TMAX −40 +85 °C 1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typical y 40 μA. In al input ranges, the input current scales with throughput. See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or VREF – 0.1 V, whichever is larger. 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. Rev. A | Page 4 of 32 Document Outline Features Functional Block Diagram Applications General Description Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Input Range Selection Input Structure Voltage Reference Input/Output Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor Power Supplies Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down Conversion Control Interfaces Digital Interface RESET Parallel Interface Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Serial Interface Data Interface Master Serial Interface Internal Clock (SER/ = High, EXT/ = Low) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) Read During Convert (RDC = High) Slave Serial Interface External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion Hardware Configuration Software Configuration Microprocessor Interfacing SPI Interface Application Information Layout Guidelines Evaluating Performance Outline Dimensions Ordering Guide