Datasheet AD9254 (Analog Devices)

14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter AD9254 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD DRVDD 1.8 V to 3.3 V output supply AD9254 SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input VIN+ 8-STAGE SFDR = 84 dBc to 70 MHz input SHA MDAC1 A/D VIN– 1 1/2-BIT PIPELINE Low power: 430 mW @ 150 MSPS 4 8 3 Differential input with 650 MHz bandwidth REFT A/D On-chip voltage reference and sample-and-hold amplifier REFB DNL = ±0.4 LSB CORRECTION LOGIC OR 15 Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS DCO Offset binary, Gray code, or twos complement data format D13 (MSB) Clock duty cycle stabilizer VREF D0 (LSB) Data output clock SENSE SCLK/DFS Serial port control 0.5V CLOCK DUTY CYCLE MODE SDIO/DCS STABILIZER SELECT Built-in selectable digital test pattern generation REF CSB SELECT Programmable clock and data alignment
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AGND CLK+ CLK– PDWN DRGND APPLICATIONS
6216 0
Ultrasound equipment
Figure 1.
IF sampling in communications receivers CDMA2000, WCDMA, TD-SCDMA, and WiMax Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes
The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided
Macro, micro, and pico cell infrastructure
to ensure proper latch timing with receiving logic.
GENERAL DESCRIPTION
The AD9254 is available in a 48-lead LFCSP_VQ and is specified The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS over the industrial temperature range (−40°C to +85°C). analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference.
PRODUCT HIGHLIGHTS
The product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 1. The AD9254 operates from a single 1.8 V power supply 150 MSPS data rates and guarantees no missing codes over the and features a separate digital output driver supply to full operating temperature range. accommodate 1.8 V to 3.3 V logic families. The wide bandwidth, truly differential SHA allows a variety of 2. The patented SHA input maintains excellent performance user-selectable input ranges and offsets, including single-ended for input frequencies up to 225 MHz. applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling 3. The clock DCS maintains overall ADC performance over a single-channel inputs at frequencies well beyond the Nyquist rate. wide range of clock pulse widths. Combined with power and cost savings over previously available 4. A standard serial port interface supports various product ADCs, the AD9254 is suitable for applications in communications, features and functions, such as data formatting (offset imaging, and medical ultrasound. binary, twos complement, or Gray coding), enabling the A differential clock input controls all internal conversion cycles. clock DCS, power-down, and voltage reference mode. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC 5. The AD9254 is pin-compatible with the AD9233, allowing performance. a simple migration from 12 bits to 14 bits.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE