Datasheet AD7634 (Analog Devices)

18-Bit, 670 kSPS, Differential Programmable Input PulSAR® ADC Data Sheet AD7634 FEATURES FUNCTIONAL BLOCK DIAGRAM Multiple pins/software-programmable input ranges TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND 5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), OVDD AGND ±10 V (40 V p-p) AD7634 REF OGND AVDD AMP Pins or serial SPI®-compatible input ranges/mode selection SERIAL DATA PDREF REF PORT Throughput PDBUF SERIAL CONFIGURATION 670 kSPS (warp mode) IN+ PORT 18 SWITCHED D[17:0] 570 kSPS (normal mode) CAP DAC IN– BUSY 450 kSPS (impulse mode) RD INL: ±1.5 LSB typical, ±2.5 LSB maximum (±9.5 ppm of FSR) PARALLEL CLOCK CS INTERFACE 18-bit resolution with no missing codes CNVST D0/OB/2C Dynamic range: 102.5 dB PD CONTROL LOGIC AND CALIBRATION CIRCUITRY D1/A0 RESET SNR: 101 dB @ 2 kHz D2/A1 THD: −112 dB @ 2kHz
1 -00
i CMOS® process technology WARP IMPULSE BIPOLAR TEN MODE0 MODE1
406 06
5 V internal reference: typical drift 3 ppm/°C; TEMP output
Figure 1.
No pipeline delay (SAR architecture) Table 1. 48-Lead PulSAR Selection Parallel (18-/16-/8-bit bus) and serial 5 V/3.3 V interface 100 to 500 to 570 to SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Res 250 570 1000 >1000 Power dissipation Input Type (Bits) (kSPS) (kSPS) (kSPS) (kSPS) 180 mW @ 670 kSPS, warp mode
Bipolar 14 AD7951
28 mW @ 100 kSPS, impulse mode
Differential 14 AD7952
10 mW @ 1 kSPS, impulse mode
Bipolar
Pb-free, 48-lead LQFP and 48-Lead LFCSP (7 mm × 7 mm)
Unipolar 16 AD7651 AD7650 AD7653 AD7660 AD7652 AD7667
APPLICATIONS
AD7661 AD7664
CT scanners
AD7666
High dynamic data acquisition
Bipolar 16 AD7610 AD7665 AD7612
Σ-Δ replacement
AD7663 AD7671
Spectrum analysis
Differential 16 AD7675 AD7676 AD7677 AD7621
Medical instruments
Unipolar AD7622 AD7623
Instrumentation Process controls
Simultaneous/ 16 AD7654 Multichannel AD7655
GENERAL DESCRIPTION
Unipolar Differential 18 AD7678 AD7679 AD7674 AD7641 The AD7634 is an 18-bit charge redistribution successive Unipolar AD7643 approximation register (SAR), architecture analog-to- Differential 18 AD7631 AD7634 digital converter (ADC) fabricated on Analog Devices, Inc.’s Bipolar iCMOS high voltage process. The device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. The AD7634 contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN−. The AD7634 features four different analog input ranges and three different sampling modes. Operation is specified from −40°C to +85°C.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V)(PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 18-Bit Interface (Master or Slave) 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (MODE[1:0] = 3, EXT/ = Low) Read During Convert (RDC = High) Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3) SLAVE SERIAL INTERFACE External Clock (MODE[1:0] = 3, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE