Datasheet AD7764 (Analog Devices) - 8

Data Sheet AD7764 Timing Diagrams 32 × tSCO t1 SCO (O) t t 2 8 t9 t3 FSO (O) t4 t t 6 5 t7 SDO (O)
002
D23 D22 D21 D20 D19 D1 D0 ST4 ST3 ST2 ST1 ST0 0 0 0
06518- Figure 2. Serial Read Timing Diagram
t1 SCO (O) t2 t12 t10 FSI (I) t11 t14 t13 t15
003
SDI (I) RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA1 RA0 D15 D14 D1 D0
06518- Figure 3. Register Write Timing Diagram
SCO (O) ≥8 × tSCO FSO (O) STATUS REGISTER DON’T CARE SDO (O) CONTENTS [31:16] BITS [15:0] NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER FSI (I)
004
SDI (I) CONTROL REGISTER CONTROL REGISTER ADDR (0x0001) INSTRUCTION
06518- Figure 4. Status Register Read Cycle Timing Diagram Rev. B | Page 7 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE