Datasheet AD9601 (Analog Devices) - 10

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AD9601 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ) B S D L D ( + – N D D – + D 3 2 1 0 O O G V D K C C K D A A A A I I C C R R V L L V D D D D N N D D D D A C C A 6 5 4 3 2 1 0 9 8 7 6 5 5 5 5 5 5 4 3 5 5 4 4 4 4 4 4 4 DA4 1 PIN 1 42 AVDD INDICATOR DA5 2 41 AVDD DA6 3 40 CML DA7 4 39 AVDD DA8 5 38 AVDD (MSB) DA9 6 37 AVDD AD9601 DRVDD 7 36 VIN– DRGND 8 TOP VIEW 35 VIN+ OVRA 9 (Not to Scale) 34 AVDD NIC 10 33 AVDD NIC 11 32 AVDD (LSB) DB0 12 31 RBIAS DB1 13 PIN 0 (EXPOSED PADDLE) = AGND 30 AVDD DB2 14 29 PWDN 5 6 7 8 0 1 1 1 1 9 1 1 2 2 22 32 42 52 62 72 82 3 4 5 6 7 8 9 B S S B T B B B B B B B D D R C F S E D D D D D D D N D D S ) V G V D/ / C E B O R R O K R
02
S D D I D L
0
M C
0-
( S S
10 07 Figure 4. Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. Mnemonic Description
30, 32, 33, 34, 37, 38, 39, AVDD 1.8 V Analog Supply. 41, 42, 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND1 Analog Ground. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 53 DA0 (LSB) Output Port A Output Bit 0 (LSB). 54 DA1 Output Port A Output Bit 1. 55 DA2 Output Port A Output Bit 2. 56 DA3 Output Port A Output Bit 3. 1 DA4 Output Port A Output Bit 4. 2 DA5 Output Port A Output Bit 5. 3 DA6 Output Port A Output Bit 6. Rev. 0 | Page 9 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE